JPS56156093A - Channel memory control system for time-division switchboard - Google Patents
Channel memory control system for time-division switchboardInfo
- Publication number
- JPS56156093A JPS56156093A JP5893280A JP5893280A JPS56156093A JP S56156093 A JPS56156093 A JP S56156093A JP 5893280 A JP5893280 A JP 5893280A JP 5893280 A JP5893280 A JP 5893280A JP S56156093 A JPS56156093 A JP S56156093A
- Authority
- JP
- Japan
- Prior art keywords
- channel
- channel memory
- writing
- control device
- external control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Abstract
PURPOSE:To realize a high speed and high multiplication with a small capacity, by reading or writing the data information given from an external control device with the other channel memory when a reading or writing is carried out with a channel memory. CONSTITUTION:A channel memory SPMO or SPM1 is selected according to whether the 6-bits information given from an external control device via an address line ADA is an even channel designation or an odd channel designation. The data information given from an incoming highway IHW is written into the 2-split channel memories SPM0 and SPM1 alternately. In case a writing is given to one of the two memories from the highway IHW, the data information from an external control device is read out or written into/out the other memory. Thus a time division is carried out.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5893280A JPS596556B2 (en) | 1980-05-02 | 1980-05-02 | Channel memory control method in time division switching equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5893280A JPS596556B2 (en) | 1980-05-02 | 1980-05-02 | Channel memory control method in time division switching equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56156093A true JPS56156093A (en) | 1981-12-02 |
JPS596556B2 JPS596556B2 (en) | 1984-02-13 |
Family
ID=13098598
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5893280A Expired JPS596556B2 (en) | 1980-05-02 | 1980-05-02 | Channel memory control method in time division switching equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS596556B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59225693A (en) * | 1983-06-06 | 1984-12-18 | Nitsuko Ltd | Time switch in time division channel |
-
1980
- 1980-05-02 JP JP5893280A patent/JPS596556B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59225693A (en) * | 1983-06-06 | 1984-12-18 | Nitsuko Ltd | Time switch in time division channel |
Also Published As
Publication number | Publication date |
---|---|
JPS596556B2 (en) | 1984-02-13 |
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