JPS5562580A - Buffer memory unit - Google Patents

Buffer memory unit

Info

Publication number
JPS5562580A
JPS5562580A JP13386778A JP13386778A JPS5562580A JP S5562580 A JPS5562580 A JP S5562580A JP 13386778 A JP13386778 A JP 13386778A JP 13386778 A JP13386778 A JP 13386778A JP S5562580 A JPS5562580 A JP S5562580A
Authority
JP
Japan
Prior art keywords
address
access
buffer memory
memory
odd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13386778A
Other languages
Japanese (ja)
Inventor
Takashi Sakai
Isao Aizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13386778A priority Critical patent/JPS5562580A/en
Publication of JPS5562580A publication Critical patent/JPS5562580A/en
Pending legal-status Critical Current

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To make it possible to take out data extending over two adjacent blocks by one access processing, by dividing and storing this data in two buffer memories and taking out it at a time by the control of a control means.
CONSTITUTION: Even-side buffer memory 1-0 and odd-side buffer memory 1-1 store even-numbered and odd-numbered blocks respectively and can be accessed independently of each other. Buffer memory address control part 5 controls selectors 4-0 and 4-1 on a basis of address information, read direction information and access length. For example, in case that the access address exists in the even side and the read direction is the address increment direction and access length is eight bytes, the access address is given to memory 1-0 as it is, and an address obtained by increasing the access address by "1" is given to memory 1-1. Thus, desired line-cross eight-byte data can be taken out at a time.
COPYRIGHT: (C)1980,JPO&Japio
JP13386778A 1978-10-31 1978-10-31 Buffer memory unit Pending JPS5562580A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13386778A JPS5562580A (en) 1978-10-31 1978-10-31 Buffer memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13386778A JPS5562580A (en) 1978-10-31 1978-10-31 Buffer memory unit

Publications (1)

Publication Number Publication Date
JPS5562580A true JPS5562580A (en) 1980-05-12

Family

ID=15114901

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13386778A Pending JPS5562580A (en) 1978-10-31 1978-10-31 Buffer memory unit

Country Status (1)

Country Link
JP (1) JPS5562580A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57172585A (en) * 1980-12-31 1982-10-23 Honeywell Inf Systems Cash-memory
JPS57172584A (en) * 1980-12-31 1982-10-23 Honeywell Inf Systems Cash-memory

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57172585A (en) * 1980-12-31 1982-10-23 Honeywell Inf Systems Cash-memory
JPS57172584A (en) * 1980-12-31 1982-10-23 Honeywell Inf Systems Cash-memory
JPH0361214B2 (en) * 1980-12-31 1991-09-19 Haneiueru Infuoomeishon Shisutemusu Inc

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