GB2011682A - Instruction buffer in computer - Google Patents

Instruction buffer in computer

Info

Publication number
GB2011682A
GB2011682A GB7850151A GB7850151A GB2011682A GB 2011682 A GB2011682 A GB 2011682A GB 7850151 A GB7850151 A GB 7850151A GB 7850151 A GB7850151 A GB 7850151A GB 2011682 A GB2011682 A GB 2011682A
Authority
GB
United Kingdom
Prior art keywords
sequence
group
transfer
cpu
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB7850151A
Other versions
GB2011682B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of GB2011682A publication Critical patent/GB2011682A/en
Application granted granted Critical
Publication of GB2011682B publication Critical patent/GB2011682B/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)

Abstract

A computer comprises a CPU, an instruction buffer, a main memory, and an associated cache memory. The instruction buffer contains 2 groups of storage locations, A and B (310 and 320). The current sequence of instructions may be stored in either. The CPU detects any transfer instruction in the current sequence and this causes the sequence following the transfer to be loaded into the other group. Thus at the cost of 2 CPU cycles, for loading the first 8 instructions of the transfer sequence in 24-instruction blocks, the CPU is able to continue processing along either the original sequence or the transfer sequence. Each group of locations (310, 320) is controlled by 2 counters, an in Counter (311, 321) for writing into the group and an Out counter (312, 322) for reading from the group. <IMAGE>
GB7850151A 1977-12-30 1978-12-28 Instructin buffer in computer Expired GB2011682B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US86608377A 1977-12-30 1977-12-30

Publications (2)

Publication Number Publication Date
GB2011682A true GB2011682A (en) 1979-07-11
GB2011682B GB2011682B (en) 1982-04-21

Family

ID=25346880

Family Applications (1)

Application Number Title Priority Date Filing Date
GB7850151A Expired GB2011682B (en) 1977-12-30 1978-12-28 Instructin buffer in computer

Country Status (5)

Country Link
JP (1) JPS5494841A (en)
AU (1) AU529675B2 (en)
DE (1) DE2856680A1 (en)
FR (1) FR2413752A1 (en)
GB (1) GB2011682B (en)

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2447078A1 (en) * 1978-12-11 1980-08-14 Honeywell Inf Systems ANTEMEMORY UNIT WITH DEVICE FOR SIMULTANEOUSLY READING INSTRUCTIONS
DE3113188A1 (en) * 1980-04-01 1981-12-03 Compagnie Internationale pour l'Informatique CII-Honeywell Bull, 75020 Paris METHOD AND DEVICE FOR CONTROLLING THE INFORMATION TRANSFER BETWEEN A STORAGE COMPLEX AND DIFFERENT PROCESSING UNITS OF A DIGITAL INFORMATION PROCESSING SYSTEM
EP0162778A2 (en) * 1984-05-21 1985-11-27 Digital Equipment Corporation Instruction prefetch system for conditional branch instruction for central processor unit
EP0323140A2 (en) * 1987-12-29 1989-07-05 Fujitsu Limited Data processing device
EP0355069A2 (en) * 1988-08-15 1990-02-21 EVANS &amp; SUTHERLAND COMPUTER CORPORATION Variable delay branch system
EP0378425A2 (en) * 1989-01-13 1990-07-18 International Business Machines Corporation Branch instruction execution apparatus
EP0448499A2 (en) * 1984-10-31 1991-09-25 International Business Machines Corporation Instruction prefetch method for branch-with-execute instructions
WO1993001545A1 (en) * 1991-07-08 1993-01-21 Seiko Epson Corporation High-performance risc microprocessor architecture
US5448705A (en) * 1991-07-08 1995-09-05 Seiko Epson Corporation RISC microprocessor architecture implementing fast trap and exception state
US5560032A (en) * 1991-07-08 1996-09-24 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution
US5961629A (en) * 1991-07-08 1999-10-05 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
US5983334A (en) * 1992-03-31 1999-11-09 Seiko Epson Corporation Superscalar microprocessor for out-of-order and concurrently executing at least two RISC instructions translating from in-order CISC instructions
EP0957428A2 (en) * 1998-05-12 1999-11-17 International Business Machines Corporation Method and apparatus for fetching noncontiguous instructions in a data processing system
US6735685B1 (en) 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US7000097B2 (en) 1992-09-29 2006-02-14 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2934771C3 (en) * 1979-08-28 1982-03-25 Siemens AG, 1000 Berlin und 8000 München Storage device.
JPS6168641A (en) * 1985-09-17 1986-04-09 Hitachi Ltd information processing equipment
EP0264077A3 (en) * 1986-10-14 1991-01-30 Honeywell Bull Inc. Buffer address register
JPH0421129A (en) * 1990-05-16 1992-01-24 Nec Corp Instruction cache device
DE19546882C2 (en) * 1995-12-15 1998-11-26 Webasto Thermosysteme Gmbh Vehicle heater

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5021821B1 (en) * 1968-10-31 1975-07-25
JPS51138355A (en) * 1975-05-26 1976-11-29 Hitachi Ltd Processing apparatus with a high speed branching feature
JPS5282149A (en) * 1975-12-29 1977-07-09 Fujitsu Ltd Instruction address control system
FR2412139B1 (en) * 1977-12-16 1986-05-09 Honeywell Inf Systems ANTEMEMORY GUIDELINES CIRCUITS

Cited By (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2447078A1 (en) * 1978-12-11 1980-08-14 Honeywell Inf Systems ANTEMEMORY UNIT WITH DEVICE FOR SIMULTANEOUSLY READING INSTRUCTIONS
DE3113188A1 (en) * 1980-04-01 1981-12-03 Compagnie Internationale pour l'Informatique CII-Honeywell Bull, 75020 Paris METHOD AND DEVICE FOR CONTROLLING THE INFORMATION TRANSFER BETWEEN A STORAGE COMPLEX AND DIFFERENT PROCESSING UNITS OF A DIGITAL INFORMATION PROCESSING SYSTEM
EP0162778A2 (en) * 1984-05-21 1985-11-27 Digital Equipment Corporation Instruction prefetch system for conditional branch instruction for central processor unit
EP0162778A3 (en) * 1984-05-21 1988-02-24 Digital Equipment Corporation Instruction prefetch system for conditional branch instruction for central processor unit
EP0448499A2 (en) * 1984-10-31 1991-09-25 International Business Machines Corporation Instruction prefetch method for branch-with-execute instructions
EP0448499A3 (en) * 1984-10-31 1992-05-06 International Business Machines Corporation Instruction prefetch method for branch-with-execute instructions
EP0323140A2 (en) * 1987-12-29 1989-07-05 Fujitsu Limited Data processing device
EP0323140A3 (en) * 1987-12-29 1991-09-25 Fujitsu Limited Data processing device
EP0355069A2 (en) * 1988-08-15 1990-02-21 EVANS &amp; SUTHERLAND COMPUTER CORPORATION Variable delay branch system
EP0355069A3 (en) * 1988-08-15 1992-07-08 EVANS &amp; SUTHERLAND COMPUTER CORPORATION Variable delay branch system
EP0378425A2 (en) * 1989-01-13 1990-07-18 International Business Machines Corporation Branch instruction execution apparatus
EP0378425A3 (en) * 1989-01-13 1992-09-02 International Business Machines Corporation Branch instruction execution apparatus
US6101594A (en) * 1991-07-08 2000-08-08 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US6986024B2 (en) 1991-07-08 2006-01-10 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5481685A (en) * 1991-07-08 1996-01-02 Seiko Epson Corporation RISC microprocessor architecture implementing fast trap and exception state
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5560032A (en) * 1991-07-08 1996-09-24 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution
US5689720A (en) * 1991-07-08 1997-11-18 Seiko Epson Corporation High-performance superscalar-based computer system with out-of-order instruction execution
US5832292A (en) * 1991-07-08 1998-11-03 Seiko Epson Corporation High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution
US5961629A (en) * 1991-07-08 1999-10-05 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
US7941635B2 (en) 1991-07-08 2011-05-10 Seiko-Epson Corporation High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution
US7555632B2 (en) 1991-07-08 2009-06-30 Seiko Epson Corporation High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution
US7162610B2 (en) 1991-07-08 2007-01-09 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US6038654A (en) * 1991-07-08 2000-03-14 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
US6038653A (en) * 1991-07-08 2000-03-14 Seiko Epson Corporation High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution
US6092181A (en) * 1991-07-08 2000-07-18 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
WO1993001545A1 (en) * 1991-07-08 1993-01-21 Seiko Epson Corporation High-performance risc microprocessor architecture
US6128723A (en) * 1991-07-08 2000-10-03 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US7028161B2 (en) 1991-07-08 2006-04-11 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution
US6272619B1 (en) 1991-07-08 2001-08-07 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US6282630B1 (en) 1991-07-08 2001-08-28 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution
US6647485B2 (en) 1991-07-08 2003-11-11 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5448705A (en) * 1991-07-08 1995-09-05 Seiko Epson Corporation RISC microprocessor architecture implementing fast trap and exception state
US6915412B2 (en) 1991-07-08 2005-07-05 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US6934829B2 (en) 1991-07-08 2005-08-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US6948052B2 (en) 1991-07-08 2005-09-20 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US6959375B2 (en) 1991-07-08 2005-10-25 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US6263423B1 (en) 1992-03-31 2001-07-17 Seiko Epson Corporation System and method for translating non-native instructions to native instructions for processing on a host processor
US6954847B2 (en) 1992-03-31 2005-10-11 Transmeta Corporation System and method for translating non-native instructions to native instructions for processing on a host processor
US7664935B2 (en) 1992-03-31 2010-02-16 Brett Coon System and method for translating non-native instructions to native instructions for processing on a host processor
US7343473B2 (en) 1992-03-31 2008-03-11 Transmeta Corporation System and method for translating non-native instructions to native instructions for processing on a host processor
US5983334A (en) * 1992-03-31 1999-11-09 Seiko Epson Corporation Superscalar microprocessor for out-of-order and concurrently executing at least two RISC instructions translating from in-order CISC instructions
US6957320B2 (en) 1992-09-29 2005-10-18 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US7000097B2 (en) 1992-09-29 2006-02-14 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US6735685B1 (en) 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US7447876B2 (en) 1992-09-29 2008-11-04 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US8019975B2 (en) 1992-09-29 2011-09-13 Seiko-Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US6965987B2 (en) 1992-09-29 2005-11-15 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US7844797B2 (en) 1992-09-29 2010-11-30 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US7861069B2 (en) 1992-09-29 2010-12-28 Seiko-Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
EP0957428A3 (en) * 1998-05-12 2000-03-08 International Business Machines Corporation Method and apparatus for fetching noncontiguous instructions in a data processing system
EP0957428A2 (en) * 1998-05-12 1999-11-17 International Business Machines Corporation Method and apparatus for fetching noncontiguous instructions in a data processing system

Also Published As

Publication number Publication date
AU4247078A (en) 1979-07-05
AU529675B2 (en) 1983-06-16
DE2856680C2 (en) 1990-05-17
JPS5494841A (en) 1979-07-26
FR2413752A1 (en) 1979-07-27
DE2856680A1 (en) 1979-08-23
GB2011682B (en) 1982-04-21
FR2413752B3 (en) 1981-10-16

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Legal Events

Date Code Title Description
PE20 Patent expired after termination of 20 years

Effective date: 19981227