JPS6168641A - Information processor - Google Patents

Abstract

PURPOSE:To decrease a frequency of instruction reading to a storage device and improve the performance by providing a buffer data register between a buffer storage device out of which one block of data is read at a time and an instruction register. CONSTITUTION:One block of 32-byte instruction is read out of the buffer storage device 2 to the buffer data register 3 in the 1st instruction reading operation. Data of buffer data registers 14 and 15 are set in instruction buffer registers 5 and 6. A selector 8 selects the 1st instruction, which is set in an instruction register 9 and decoded. When the instructions in the instruction buffer register 5 are all decoded, the instruction selection moves to the instruction buffer register 6. While the instructions in the register 6 are processed, the next instruction in the buffer data register 16 is set in the register 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an information processing device that sequentially retrieves and executes instructions from a storage device.

[Background of the invention]

In conventional information processing devices, if two or more different read requests from the storage device cannot be processed simultaneously, the instruction read and the operand read required by the instruction collide in the storage control unit, causing one of them to wait, resulting in the instruction This resulted in a decrease in performance.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a means for simultaneously processing two or more different read requests from a storage device (by reducing conflicts between instruction read and operand read and preventing performance degradation).

[Summary of the invention]

In terms of instruction performance, it has become impossible to overlook the deterioration in performance due to conflict between instruction reading and operand reading/reading required by the instruction.

The present invention was devised based on the idea that it is possible to reduce the performance deterioration caused by this collision K even a little.

[Embodiments of the invention]

FIG. 1 shows an example of a conventional system, and FIG. 2 shows an embodiment of the present invention. For convenience of explanation, the data width in Figures 1 and 2 is 8 bytes, and 1 block of the puff 7 storage device in Figure 2 is 3
2 bytes, 4 instruction buffer registers are 8 bytes wide and 2
Individual. Furthermore, it is assumed that the beginning of the instruction is on a 32-byte boundary and exists within the buffer storage.

In FIG. 1, instructions are read from 20 buffer 7 storage devices and transferred to 5 instruction buffer registers O via 3 buffer 7 data registers. Further, the next 8-byte instruction that is subsequently read out is also transferred to the 6th instruction buffer register l via the 30th buffer data register.

The instruction is set in the instruction buffer register 0 of 5 and the money and 8 are set.
The selector causes the first command to be Sereno.

is written and set in instruction register 9. When the instruction set in instruction register 9 has been decoded, the next instruction is selected from instruction buffer register 5 in instruction register 9. In this way, the instructions progress one after another, and when all the instructions in the instruction buffer register 0 side of 5 are selected, the instruction selection moves to the instruction buffer register l side of 6, and the instruction in the instruction buffer register l side of 6 is executed. During this time, the next instruction is read from the buffer storage device and set in the vacant 5 instruction buffer register 0 side via the 30 buffer data register.

As described above, the instructions set in the instruction buffer 7 register are sequentially selected and executed, and when one instruction buffer register is executed, the instruction is read and set in a vacant instruction buffer register. If this method is used, and furthermore, two or more reads from the storage device cannot be processed at the same time, and the instruction is 4 bytes wide and requires one operand read, and this instruction can be processed continuously every machine cycle, then 3 The operand read of the instruction will collide with the instruction read.

In the present invention, as shown in FIG.
The objective is to reduce the time occupied by the storage device by reading instructions by having four 8-byte width 3 buffer data registers under which one block of data issued by the reader can be set.

Assuming that the instructions are stored in the buffer storage device No. 2 as described above, the first instruction read will read one block of 32-byte instructions from the buffer storage device No. 3, and the instructions will be stored in the buffer data registers No. 14-17. The data of the buffer data registers 0.1 of 14 and 15 are set in the instruction buffer 7 registers of 5 and 6. When the instruction buffer register 04C instruction 5 is set, the first instruction is selected by the selector 8 and set in the instruction register 9, and decoding of the instruction begins. When the instruction has been decoded, the next instruction is selected from the instruction buffer register 7 in the instruction register 9, and the instructions are decoded one after another. When all of the instructions in the instruction buffer 7 register θ of 5 are selected to the instruction register 9, the instruction select moves to the instruction buffer register 1 of 6. While processing the instruction in 6's instruction buffer 7 register 1, 5's instruction buffer register O
Sets data from buffer 7 data register 2 of 16 where the next instruction is. When all the instructions in the instruction buffer register 1 of No. 6 are selected and set in the instruction register No. 9, the next instruction is again supplied with instructions from the instruction buffer register O of No. 5. During this time, data is set in the instruction buffer V register 1 of 6 from the buffer data register 3 of 17 in which the next instruction is located. When all the data in data buffer 7 registers O to 3 of 14-17 are transferred to instruction buffer registers 0 and 1 of 5 and 6, an instruction read occurs here, and 1 block of 32-byte data is read again from the buffer storage device of 2. 3 data buffer 7 register.

When all the instructions in instruction buffer register 0 of 5 are selected again to instruction register 9, 14 with the new instruction is selected.
Receives instructions from data buffer register 0 of .

In this way, instruction buffer 7 register 0.5 and 6. IK receives instruction data sequentially from buffer 7 data registers θ to 3 of 14-17. This causes the above command to be 4
Assuming that the instruction has a byte width and requires one operand read and can be processed continuously every machine cycle, the ninth instruction's operand read and instruction read will collide.

As explained above, in the conventional method shown in FIG. 1 and the embodiment of the present invention shown in FIG. There is.

〔Effect of the invention〕

According to the present invention, as described above, it is possible to reduce the number of times instructions are read to the storage device, so there is an effect of reducing the rate of performance deterioration.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the conventional instruction read route;
The figure is a block diagram of an instruction read route according to the present invention. l...Buffer storage write data register. 2...Buffer storage it. 3...Buffer 7 data register. 4...Instruction buffer register. 5...Instruction buffer register 0゜6...Instruction buffer register 1゜7...Oherandshaft register. 8...Selector, 9...Instruction register. 10-13...Buffer storage bank O-3゜14
~17...Buffer data register O-3゜years old 1
Kouji = To 9 years old 2 years old Figure

Claims (1)

[Claims] 1. In an information processing device that sequentially reads and executes instructions from a storage device, there is a buffer storage device that can read one block of data at a time, a register that temporarily stores instructions, and a buffer storage device, where the data is read from the buffer storage device. 1. An information processing device having a register for temporarily storing one block of data, and sequentially transferring instructions from the one block data register to the temporarily storing register.