JPS5494841A - Data processing system having instruction buffer relative to cache memory - Google Patents

Data processing system having instruction buffer relative to cache memory

Info

Publication number
JPS5494841A
JPS5494841A JP15678478A JP15678478A JPS5494841A JP S5494841 A JPS5494841 A JP S5494841A JP 15678478 A JP15678478 A JP 15678478A JP 15678478 A JP15678478 A JP 15678478A JP S5494841 A JPS5494841 A JP S5494841A
Authority
JP
Japan
Prior art keywords
data processing
processing system
cache memory
instruction buffer
buffer relative
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15678478A
Other languages
Japanese (ja)
Inventor
Ii Uiruhaito Jiyon
Ei Shierii Uiriamu
Pii Raian Chiyaaruzu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Original Assignee
Honeywell Information Systems Italia SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA filed Critical Honeywell Information Systems Italia SpA
Publication of JPS5494841A publication Critical patent/JPS5494841A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
JP15678478A 1977-12-30 1978-12-19 Data processing system having instruction buffer relative to cache memory Pending JPS5494841A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US86608377A 1977-12-30 1977-12-30

Publications (1)

Publication Number Publication Date
JPS5494841A true JPS5494841A (en) 1979-07-26

Family

ID=25346880

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15678478A Pending JPS5494841A (en) 1977-12-30 1978-12-19 Data processing system having instruction buffer relative to cache memory

Country Status (5)

Country Link
JP (1) JPS5494841A (en)
AU (1) AU529675B2 (en)
DE (1) DE2856680A1 (en)
FR (1) FR2413752A1 (en)
GB (1) GB2011682B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6168641A (en) * 1985-09-17 1986-04-09 Hitachi Ltd Information processor
JPH0421129A (en) * 1990-05-16 1992-01-24 Nec Corp Instruction cache device

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2072905B (en) * 1978-12-11 1983-08-03 Honeywell Inf Systems Data-processing apparatus
DE2934771C3 (en) * 1979-08-28 1982-03-25 Siemens AG, 1000 Berlin und 8000 München Storage device.
FR2479532B1 (en) * 1980-04-01 1986-09-19 Bull Sa METHOD AND DEVICE FOR MANAGING THE TRANSFER OF INFORMATION BETWEEN A MEMORY SET AND THE DIFFERENT PROCESSING UNITS OF A DIGITAL INFORMATION PROCESSING SYSTEM
US4742451A (en) * 1984-05-21 1988-05-03 Digital Equipment Corporation Instruction prefetch system for conditional branch instruction for central processor unit
US4775927A (en) * 1984-10-31 1988-10-04 International Business Machines Corporation Processor including fetch operation for branch instruction with control tag
EP0264077A3 (en) * 1986-10-14 1991-01-30 Honeywell Bull Inc. Buffer address register
JPH0769812B2 (en) * 1987-12-29 1995-07-31 富士通株式会社 Data processing device
US4974155A (en) * 1988-08-15 1990-11-27 Evans & Sutherland Computer Corp. Variable delay branch system
US5127091A (en) * 1989-01-13 1992-06-30 International Business Machines Corporation System for reducing delay in instruction execution by executing branch instructions in separate processor while dispatching subsequent instructions to primary processor
EP1526446A3 (en) 1991-07-08 2007-04-04 Seiko Epson Corporation Extensible RISC microprocessor architecture
EP0547240B1 (en) * 1991-07-08 2000-01-12 Seiko Epson Corporation Risc microprocessor architecture implementing fast trap and exception state
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5961629A (en) * 1991-07-08 1999-10-05 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
US5438668A (en) 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
US6735685B1 (en) 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
KR100248903B1 (en) 1992-09-29 2000-03-15 야스카와 히데아키 System and method for handling load and/or store operating in a superscalar microprocessor
DE19546882C2 (en) * 1995-12-15 1998-11-26 Webasto Thermosysteme Gmbh Vehicle heater
US6256727B1 (en) * 1998-05-12 2001-07-03 International Business Machines Corporation Method and system for fetching noncontiguous instructions in a single clock cycle

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51138355A (en) * 1975-05-26 1976-11-29 Hitachi Ltd Processing apparatus with a high speed branching feature
JPS5282149A (en) * 1975-12-29 1977-07-09 Fujitsu Ltd Instruction address control system

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5021821B1 (en) * 1968-10-31 1975-07-25
CA1116756A (en) * 1977-12-16 1982-01-19 Charles P. Ryan Cache memory command circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51138355A (en) * 1975-05-26 1976-11-29 Hitachi Ltd Processing apparatus with a high speed branching feature
JPS5282149A (en) * 1975-12-29 1977-07-09 Fujitsu Ltd Instruction address control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6168641A (en) * 1985-09-17 1986-04-09 Hitachi Ltd Information processor
JPH0421129A (en) * 1990-05-16 1992-01-24 Nec Corp Instruction cache device

Also Published As

Publication number Publication date
AU4247078A (en) 1979-07-05
AU529675B2 (en) 1983-06-16
GB2011682B (en) 1982-04-21
DE2856680A1 (en) 1979-08-23
FR2413752B3 (en) 1981-10-16
DE2856680C2 (en) 1990-05-17
GB2011682A (en) 1979-07-11
FR2413752A1 (en) 1979-07-27

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