JPS57199060A - Address controlling device - Google Patents
Address controlling deviceInfo
- Publication number
- JPS57199060A JPS57199060A JP56083465A JP8346581A JPS57199060A JP S57199060 A JPS57199060 A JP S57199060A JP 56083465 A JP56083465 A JP 56083465A JP 8346581 A JP8346581 A JP 8346581A JP S57199060 A JPS57199060 A JP S57199060A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- stored
- register
- added
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE:To reduce failures on a program, by transferring an object program having relocatable information to a memory at high speed. CONSTITUTION:An input data block is stored in a data register DR101 and the record length and the phrase length are respectively counted at a master counter 103 and an SC counter 105 and checked. A designated relocation address is stored in a relocation register RR113, this address AD and the AD of the input data are added 118, and the linkage word LK between the added output and the input data is stored in an LK memory 106. The LK word from the memory 106 and the output of a register 109 requiring the LK are compared 119, and if coincident, an LKAD from the memory 106 and the modified data from a DR 101 are added 120. The result of addition is stored in a DR114 and transferred to a storage device, and the content of a memory ADR115 storing the output of the RR113 is renewed at each transfer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56083465A JPS57199060A (en) | 1981-05-30 | 1981-05-30 | Address controlling device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56083465A JPS57199060A (en) | 1981-05-30 | 1981-05-30 | Address controlling device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57199060A true JPS57199060A (en) | 1982-12-06 |
Family
ID=13803211
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56083465A Pending JPS57199060A (en) | 1981-05-30 | 1981-05-30 | Address controlling device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57199060A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63317824A (en) * | 1987-06-22 | 1988-12-26 | Mitsubishi Electric Corp | Program starting system |
-
1981
- 1981-05-30 JP JP56083465A patent/JPS57199060A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63317824A (en) * | 1987-06-22 | 1988-12-26 | Mitsubishi Electric Corp | Program starting system |
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