SE8001908L - DATABEHANDLINGSANLEGGNING - Google Patents
DATABEHANDLINGSANLEGGNINGInfo
- Publication number
- SE8001908L SE8001908L SE8001908A SE8001908A SE8001908L SE 8001908 L SE8001908 L SE 8001908L SE 8001908 A SE8001908 A SE 8001908A SE 8001908 A SE8001908 A SE 8001908A SE 8001908 L SE8001908 L SE 8001908L
- Authority
- SE
- Sweden
- Prior art keywords
- bus
- units
- unit
- predetermined number
- clock pulses
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
- G06F13/374—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a self-select method with individual priority code comparator
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
- G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Multi Processors (AREA)
- Microcomputers (AREA)
- Information Transfer Systems (AREA)
- Memory System (AREA)
Abstract
In a data processing system central processor units (10 and 10A), input/ output units (12), memory units (11) and secondary storage units (24, 25, and 26, 27) are interconnected by a bus (14). When one of the units, for example the processor unit (10), is to transfer information to a second unit, for example the controller (20) of the memory units (11) over the bus (14), the first unit, to prevent other units gaining access to the bus, generates a first signal onto a line in the bus (14) for a predetermined number of clock pulses, e.g. one cycle conflicting requests for bus access being resolved by priority arrangements. The second unit then takes over generation of the first signal on the bus line after the predetermined number of clock pulses up to the end of the transfer. <IMAGE>
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US1935179A | 1979-03-12 | 1979-03-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SE8001908L true SE8001908L (en) | 1980-09-13 |
Family
ID=21792737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SE8001908A SE8001908L (en) | 1979-03-12 | 1980-03-11 | DATABEHANDLINGSANLEGGNING |
Country Status (10)
| Country | Link |
|---|---|
| JP (1) | JPS6051151B2 (en) |
| AU (1) | AU542538B2 (en) |
| BR (1) | BR8001527A (en) |
| CA (1) | CA1143853A (en) |
| DE (1) | DE3009529A1 (en) |
| ES (1) | ES489424A0 (en) |
| FR (1) | FR2451601A1 (en) |
| GB (1) | GB2044967A (en) |
| IT (1) | IT1129639B (en) |
| SE (1) | SE8001908L (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU576348B2 (en) * | 1984-02-29 | 1988-08-25 | Measurex Corporation | Processing information |
| US4669056A (en) * | 1984-07-31 | 1987-05-26 | International Business Machines Corporation | Data processing system with a plurality of processors accessing a common bus to interleaved storage |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US2997896A (en) * | 1958-10-08 | 1961-08-29 | Preston Martin | Variable speed drives |
| US3999170A (en) * | 1975-01-08 | 1976-12-21 | Hewlett-Packard Company | Multiple access interconnect system |
| JPS6035698B2 (en) * | 1977-10-25 | 1985-08-16 | デイジタル イクイプメント コ−ポレ−シヨン | data processing system |
-
1980
- 1980-03-11 ES ES489424A patent/ES489424A0/en active Granted
- 1980-03-11 SE SE8001908A patent/SE8001908L/en not_active Application Discontinuation
- 1980-03-12 IT IT20544/80A patent/IT1129639B/en active
- 1980-03-12 DE DE19803009529 patent/DE3009529A1/en not_active Withdrawn
- 1980-03-12 BR BR8001527A patent/BR8001527A/en unknown
- 1980-03-12 FR FR8005575A patent/FR2451601A1/en active Pending
- 1980-03-12 AU AU56376/80A patent/AU542538B2/en not_active Ceased
- 1980-03-12 CA CA000347498A patent/CA1143853A/en not_active Expired
- 1980-03-12 GB GB8008339A patent/GB2044967A/en not_active Withdrawn
- 1980-03-12 JP JP55031490A patent/JPS6051151B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| CA1143853A (en) | 1983-03-29 |
| IT1129639B (en) | 1986-06-11 |
| JPS6051151B2 (en) | 1985-11-12 |
| ES8103407A1 (en) | 1981-02-16 |
| ES489424A0 (en) | 1981-02-16 |
| FR2451601A1 (en) | 1980-10-10 |
| BR8001527A (en) | 1980-11-11 |
| AU5637680A (en) | 1980-09-18 |
| GB2044967A (en) | 1980-10-22 |
| AU542538B2 (en) | 1985-02-28 |
| JPS55134427A (en) | 1980-10-20 |
| IT8020544A0 (en) | 1980-03-12 |
| DE3009529A1 (en) | 1980-09-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| NAV | Patent application has lapsed |
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