JPS56168251A - Data transfer buffer system - Google Patents

Data transfer buffer system

Info

Publication number
JPS56168251A
JPS56168251A JP7207080A JP7207080A JPS56168251A JP S56168251 A JPS56168251 A JP S56168251A JP 7207080 A JP7207080 A JP 7207080A JP 7207080 A JP7207080 A JP 7207080A JP S56168251 A JPS56168251 A JP S56168251A
Authority
JP
Japan
Prior art keywords
data transfer
register
buffer
substituting
address register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7207080A
Other languages
Japanese (ja)
Inventor
Seiichi Sugaya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7207080A priority Critical patent/JPS56168251A/en
Publication of JPS56168251A publication Critical patent/JPS56168251A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory

Abstract

PURPOSE:To improve the reliability of data transfer by preparing substituting areas for a data buffer memory for the purpose of data transfer. CONSTITUTION:Substituting buffer registers 1b, 1c, 1d having the same capacity as that of a buffer register 1a are provided and the 3rd address register 10 is added. The initial value of the addrss register 10 is a ''0'', and data transfer is started by using the buffer register 1a corresponding to this. These are so controlled that when an error is detected in the data read out from the buffer register 1a, the address register 10 is stepped, and at the next data transfer, the substituting buffer register 1b is used. The address register 2 is used for data transfer to and form a main storage device, and the address register 3 is used for data transfer to and from input/output devices.
JP7207080A 1980-05-29 1980-05-29 Data transfer buffer system Pending JPS56168251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7207080A JPS56168251A (en) 1980-05-29 1980-05-29 Data transfer buffer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7207080A JPS56168251A (en) 1980-05-29 1980-05-29 Data transfer buffer system

Publications (1)

Publication Number Publication Date
JPS56168251A true JPS56168251A (en) 1981-12-24

Family

ID=13478767

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7207080A Pending JPS56168251A (en) 1980-05-29 1980-05-29 Data transfer buffer system

Country Status (1)

Country Link
JP (1) JPS56168251A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4772920B2 (en) * 2008-05-30 2011-09-14 株式会社アドバンテスト Test apparatus and transmission apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4772920B2 (en) * 2008-05-30 2011-09-14 株式会社アドバンテスト Test apparatus and transmission apparatus
KR101215388B1 (en) 2008-05-30 2012-12-26 가부시키가이샤 어드밴티스트 Testing equipment and transmitter
US8407532B2 (en) 2008-05-30 2013-03-26 Advantest Corporation Test apparatus and transmission device

Similar Documents

Publication Publication Date Title
JPS55129847A (en) Access system of memory unit
JPS5690341A (en) Buffer switching system
JPS56168251A (en) Data transfer buffer system
JPS52139333A (en) Data input system for cash register
JPS5363935A (en) Memory address control system
JPS57127997A (en) Semiconductor integrated storage device
JPS5745639A (en) Data transfer control system
JPS5720831A (en) Local burst transfer controlling system
JPS526032A (en) Main storage control unit
JPS56149626A (en) Channel device
JPS5733472A (en) Memory access control system
JPS5466732A (en) Data buffer control unit in data transfer unit
JPS5638631A (en) Data transfer apparatus
JPS5533282A (en) Buffer control system
JPS56146344A (en) Terminal control device
JPS52106642A (en) Data transfer unit
JPS55105884A (en) Address conversion device
JPS5750378A (en) Control system of data processor
JPS56114026A (en) Data processor
JPS57199060A (en) Address controlling device
JPS57176464A (en) Data transfer system
JPS5294040A (en) Data processing unit
JPS51116634A (en) Input output control unit
JPS56114056A (en) Memory device for pointer-type data
JPS5393740A (en) Data input/output device