JPS57176464A - Data transfer system - Google Patents

Data transfer system

Info

Publication number
JPS57176464A
JPS57176464A JP6208181A JP6208181A JPS57176464A JP S57176464 A JPS57176464 A JP S57176464A JP 6208181 A JP6208181 A JP 6208181A JP 6208181 A JP6208181 A JP 6208181A JP S57176464 A JPS57176464 A JP S57176464A
Authority
JP
Japan
Prior art keywords
memory
section
data
write
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6208181A
Other languages
Japanese (ja)
Inventor
Tsuneyoshi Muranaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP6208181A priority Critical patent/JPS57176464A/en
Publication of JPS57176464A publication Critical patent/JPS57176464A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing

Abstract

PURPOSE:To make data transfer in a memory directly in high speed possible, by splitting a memory having a longer characteristic than an access time at least into two units as for the memory cycle. CONSTITUTION:The system consists of a memory section 4 which makes data write/read according to the state of a memory selection signal SEL given from a control section 3 by taking an output of an adder 2 adding an offset signal and a memory address designation as a real address and a memory write signal WR, and a memory section 5 which is directly accessed with the same memory address designation and makes write/read of data according to the state of a signal SEL2 given from a CPU and a memory write signal WR'. For example, in reading out of data in the address A of the memory section 5, memory elements having longer memory access time than the memory cycle time are used as the memory sections 4 and 5, and the readout data is written in the memory section 4 before one memory cycle is finished.
JP6208181A 1981-04-24 1981-04-24 Data transfer system Pending JPS57176464A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6208181A JPS57176464A (en) 1981-04-24 1981-04-24 Data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6208181A JPS57176464A (en) 1981-04-24 1981-04-24 Data transfer system

Publications (1)

Publication Number Publication Date
JPS57176464A true JPS57176464A (en) 1982-10-29

Family

ID=13189752

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6208181A Pending JPS57176464A (en) 1981-04-24 1981-04-24 Data transfer system

Country Status (1)

Country Link
JP (1) JPS57176464A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6132290A (en) * 1984-07-24 1986-02-14 Matsushita Electric Ind Co Ltd Memory device
JPS62214452A (en) * 1986-03-17 1987-09-21 Mitsubishi Electric Corp Memory control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6132290A (en) * 1984-07-24 1986-02-14 Matsushita Electric Ind Co Ltd Memory device
JPS62214452A (en) * 1986-03-17 1987-09-21 Mitsubishi Electric Corp Memory control system

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