JPS54124644A - Data transfer system - Google Patents

Data transfer system

Info

Publication number
JPS54124644A
JPS54124644A JP3106378A JP3106378A JPS54124644A JP S54124644 A JPS54124644 A JP S54124644A JP 3106378 A JP3106378 A JP 3106378A JP 3106378 A JP3106378 A JP 3106378A JP S54124644 A JPS54124644 A JP S54124644A
Authority
JP
Japan
Prior art keywords
processing unit
memory
data
controller
program
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3106378A
Other languages
Japanese (ja)
Inventor
Mamoru Araya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3106378A priority Critical patent/JPS54124644A/en
Publication of JPS54124644A publication Critical patent/JPS54124644A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the number of program start times to improve a data transfer efficiency by performing alternately two-way data transfers between a processing unit and an I/O controller in one WORD unit by a one-time program instruction.
CONSTITUTION: At a program start time, the start address of a memory, which data should be transferred to, in a processing unit and the number of transfer words are preset in READ-direction and WRITE-direction registers 14, 15, 16 and 17 provided in I/O controller 2. While designating memory addresses by I/O controller 2, READ and WRITE operations are repeated alternately by direct memory access start instructions. Then, operations for writing data in receiving buffer register 13 to the memory of the processing unit and reading data from the memory in the processing unit into transmission buffer register 12 are performed alternately in the same program mode.
COPYRIGHT: (C)1979,JPO&Japio
JP3106378A 1978-03-20 1978-03-20 Data transfer system Pending JPS54124644A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3106378A JPS54124644A (en) 1978-03-20 1978-03-20 Data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3106378A JPS54124644A (en) 1978-03-20 1978-03-20 Data transfer system

Publications (1)

Publication Number Publication Date
JPS54124644A true JPS54124644A (en) 1979-09-27

Family

ID=12321001

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3106378A Pending JPS54124644A (en) 1978-03-20 1978-03-20 Data transfer system

Country Status (1)

Country Link
JP (1) JPS54124644A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63143603A (en) * 1986-12-05 1988-06-15 Omron Tateisi Electronics Co Programmable controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63143603A (en) * 1986-12-05 1988-06-15 Omron Tateisi Electronics Co Programmable controller
JP2508038B2 (en) * 1986-12-05 1996-06-19 オムロン株式会社 Programmable controller

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