JPS5463640A - Information processing system - Google Patents

Information processing system

Info

Publication number
JPS5463640A
JPS5463640A JP12989777A JP12989777A JPS5463640A JP S5463640 A JPS5463640 A JP S5463640A JP 12989777 A JP12989777 A JP 12989777A JP 12989777 A JP12989777 A JP 12989777A JP S5463640 A JPS5463640 A JP S5463640A
Authority
JP
Japan
Prior art keywords
memory
facilities
count
cpu
information processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12989777A
Other languages
Japanese (ja)
Inventor
Hideyuki Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12989777A priority Critical patent/JPS5463640A/en
Publication of JPS5463640A publication Critical patent/JPS5463640A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enhance the effeciency of the informaion processing system by using a dedicated processing module in case of data transfer of memory contents to reduce the load of CPU.
CONSTITUTION: In the information processing system where memory 3 and I/0 devices are connected to CPU 1 through bus line 2, memory data moving controller 4 is connected. In this controller 4, data register 5 which stores data read from memory 3 and data written to memory 3, address registers 6 and 7 which are equipped with the count facilities to store addresses, and length register 8 which is equipped with the count facilities to store the move quantity of memory 3 are provided. Further, bus interface 9 which is located between bus line 2 and these registers 5 to 8 and controls the count facilities, which registers 5 to 8 have, and repeats the move operation until contents of the counter reach zero is also provided, thus performing the information processing by analyzing the move instruction issued from CPU 1.
COPYRIGHT: (C)1979,JPO&Japio
JP12989777A 1977-10-29 1977-10-29 Information processing system Pending JPS5463640A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12989777A JPS5463640A (en) 1977-10-29 1977-10-29 Information processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12989777A JPS5463640A (en) 1977-10-29 1977-10-29 Information processing system

Publications (1)

Publication Number Publication Date
JPS5463640A true JPS5463640A (en) 1979-05-22

Family

ID=15021063

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12989777A Pending JPS5463640A (en) 1977-10-29 1977-10-29 Information processing system

Country Status (1)

Country Link
JP (1) JPS5463640A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58502072A (en) * 1981-12-04 1983-12-01 バロ−ス・コ−ポレ−ション Data processing system providing improved data transfer between modules
JPH03240854A (en) * 1990-11-21 1991-10-28 Hitachi Ltd Microcomputer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58502072A (en) * 1981-12-04 1983-12-01 バロ−ス・コ−ポレ−ション Data processing system providing improved data transfer between modules
JPH03240854A (en) * 1990-11-21 1991-10-28 Hitachi Ltd Microcomputer
JPH0638249B2 (en) * 1990-11-21 1994-05-18 株式会社日立製作所 Microcomputer

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