JPS55123739A - Memory content prefetch control system - Google Patents

Memory content prefetch control system

Info

Publication number
JPS55123739A
JPS55123739A JP3029079A JP3029079A JPS55123739A JP S55123739 A JPS55123739 A JP S55123739A JP 3029079 A JP3029079 A JP 3029079A JP 3029079 A JP3029079 A JP 3029079A JP S55123739 A JPS55123739 A JP S55123739A
Authority
JP
Japan
Prior art keywords
unit
memory
perform
data processing
latch circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3029079A
Other languages
Japanese (ja)
Inventor
Tomohito Shibata
Masaaki Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3029079A priority Critical patent/JPS55123739A/en
Publication of JPS55123739A publication Critical patent/JPS55123739A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to perform the data processing efficiently, by causing a latch circuit, etc., to perform the read access to a memory to prefetch memory contents.
CONSTITUTION: In the data processing unit equipped with a microprocessor which has no memory prefetch function, memory access control unit 3 is connected to CPU1 through common bus 2, and memories 5-1, 5-2... are accessed by this unit 3. Here, unit 3 utilizes the idle time, when CPU1 performs the memory access to perform the read access to memories 5-1, 5-2... dependently upon address latch circuit 7, address comparing circuit 8, read data latch circuit 10, etc., which are provided in unit 3, thus prefetching memory contents. By this operation, needless frefetch generated for branch instructions is stopped, and the response of unit 3 is made rapid to release occupation of bus 2, thereby performing the data processing efficiently.
COPYRIGHT: (C)1980,JPO&Japio
JP3029079A 1979-03-15 1979-03-15 Memory content prefetch control system Pending JPS55123739A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3029079A JPS55123739A (en) 1979-03-15 1979-03-15 Memory content prefetch control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3029079A JPS55123739A (en) 1979-03-15 1979-03-15 Memory content prefetch control system

Publications (1)

Publication Number Publication Date
JPS55123739A true JPS55123739A (en) 1980-09-24

Family

ID=12299585

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3029079A Pending JPS55123739A (en) 1979-03-15 1979-03-15 Memory content prefetch control system

Country Status (1)

Country Link
JP (1) JPS55123739A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58205258A (en) * 1982-05-24 1983-11-30 Matsushita Electric Ind Co Ltd Data processor
JPS5957348A (en) * 1982-08-26 1984-04-02 Fujitsu Ltd System for inhibiting extraction of instruction and cancellig inhibition in information processor
JPS59111545A (en) * 1982-12-17 1984-06-27 Fuji Electric Co Ltd Information processor
JPS59202867A (en) * 1983-05-04 1984-11-16 Sanyo Electric Co Ltd Printing control apparatus
JPS59202870A (en) * 1983-05-04 1984-11-16 Sanyo Electric Co Ltd Printing controller
JPS59202871A (en) * 1983-05-04 1984-11-16 Sanyo Electric Co Ltd Printing controller
JPS59202868A (en) * 1983-05-04 1984-11-16 Sanyo Electric Co Ltd Printing control apparatus
JPS61211744A (en) * 1985-03-18 1986-09-19 Nec Corp Instruction prefetch control circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5039427A (en) * 1973-08-10 1975-04-11
JPS5136037A (en) * 1974-09-21 1976-03-26 Hitachi Ltd MEMORISEIGYO HOSHIKI
JPS5140824A (en) * 1974-10-04 1976-04-06 Hitachi Ltd

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5039427A (en) * 1973-08-10 1975-04-11
JPS5136037A (en) * 1974-09-21 1976-03-26 Hitachi Ltd MEMORISEIGYO HOSHIKI
JPS5140824A (en) * 1974-10-04 1976-04-06 Hitachi Ltd

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58205258A (en) * 1982-05-24 1983-11-30 Matsushita Electric Ind Co Ltd Data processor
JPS5957348A (en) * 1982-08-26 1984-04-02 Fujitsu Ltd System for inhibiting extraction of instruction and cancellig inhibition in information processor
JPS6235694B2 (en) * 1982-08-26 1987-08-03 Fujitsu Ltd
JPS59111545A (en) * 1982-12-17 1984-06-27 Fuji Electric Co Ltd Information processor
JPH059817B2 (en) * 1982-12-17 1993-02-08 Fuji Denki Kk
JPS59202868A (en) * 1983-05-04 1984-11-16 Sanyo Electric Co Ltd Printing control apparatus
JPS59202871A (en) * 1983-05-04 1984-11-16 Sanyo Electric Co Ltd Printing controller
JPS59202870A (en) * 1983-05-04 1984-11-16 Sanyo Electric Co Ltd Printing controller
JPH021676B2 (en) * 1983-05-04 1990-01-12 Sanyo Electric Co
JPH023714B2 (en) * 1983-05-04 1990-01-24 Sanyo Electric Co
JPH0356189B2 (en) * 1983-05-04 1991-08-27
JPS59202867A (en) * 1983-05-04 1984-11-16 Sanyo Electric Co Ltd Printing control apparatus
JPS61211744A (en) * 1985-03-18 1986-09-19 Nec Corp Instruction prefetch control circuit

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