JPS5657111A - Sequence controller - Google Patents
Sequence controllerInfo
- Publication number
- JPS5657111A JPS5657111A JP13271579A JP13271579A JPS5657111A JP S5657111 A JPS5657111 A JP S5657111A JP 13271579 A JP13271579 A JP 13271579A JP 13271579 A JP13271579 A JP 13271579A JP S5657111 A JPS5657111 A JP S5657111A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- read
- write
- bit operation
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Programmable Controllers (AREA)
Abstract
PURPOSE: To use a general microprocessor having no bit operation function to execute the bit operation processing in a high speed, by providing a prescribed data memory.
CONSTITUTION: Data memory 10 consisting of read/write memory part 11 and memory control part 12 is provided besides microprocessor 3, program memory 2, and input/output device 1. This memory 10 is connected to processor 3 through data bus 101 and address bus 103. Write and read of the word unit are performed in memory 10 by designation of the address signal, and memory 10 is so formed that write and read for a specific (the most significant) bit on the data bus are possible. Consequently, word operation and bit operation can be executed directly by machine language instructions of processor 3. Thus, general processor 3 is used to execute the bit operation in a high speed.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13271579A JPS5657111A (en) | 1979-10-15 | 1979-10-15 | Sequence controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13271579A JPS5657111A (en) | 1979-10-15 | 1979-10-15 | Sequence controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5657111A true JPS5657111A (en) | 1981-05-19 |
Family
ID=15087878
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13271579A Pending JPS5657111A (en) | 1979-10-15 | 1979-10-15 | Sequence controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5657111A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59133607A (en) * | 1983-01-19 | 1984-08-01 | Fuji Facom Corp | Process controller |
JPS6031645A (en) * | 1983-08-01 | 1985-02-18 | Hitachi Ltd | Central processing unit |
JPS6335104U (en) * | 1986-08-26 | 1988-03-07 | ||
US5121490A (en) * | 1986-01-22 | 1992-06-09 | Hitachi, Ltd. | Bit and word memory allocation for a programmable controller |
-
1979
- 1979-10-15 JP JP13271579A patent/JPS5657111A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59133607A (en) * | 1983-01-19 | 1984-08-01 | Fuji Facom Corp | Process controller |
JPS6031645A (en) * | 1983-08-01 | 1985-02-18 | Hitachi Ltd | Central processing unit |
JPH0414362B2 (en) * | 1983-08-01 | 1992-03-12 | Hitachi Ltd | |
US5121490A (en) * | 1986-01-22 | 1992-06-09 | Hitachi, Ltd. | Bit and word memory allocation for a programmable controller |
JPS6335104U (en) * | 1986-08-26 | 1988-03-07 |
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