JPS5688523A - Data processor - Google Patents

Data processor

Info

Publication number
JPS5688523A
JPS5688523A JP16642579A JP16642579A JPS5688523A JP S5688523 A JPS5688523 A JP S5688523A JP 16642579 A JP16642579 A JP 16642579A JP 16642579 A JP16642579 A JP 16642579A JP S5688523 A JPS5688523 A JP S5688523A
Authority
JP
Japan
Prior art keywords
processor
μpc22
processing
speed
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16642579A
Other languages
Japanese (ja)
Inventor
Kazuyuki Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP16642579A priority Critical patent/JPS5688523A/en
Publication of JPS5688523A publication Critical patent/JPS5688523A/en
Pending legal-status Critical Current

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  • Microcomputers (AREA)

Abstract

PURPOSE: To shorten the execution time of instructions when a high-speed processor is used, by quickening data transfer between microprocessor μPC and the high-speed processor.
CONSTITUTION: When fetching a high-speed processing instruction from main memory 26, μPC22 starts a corresponding microprogram and permits high-speed processor 27 to perform high-speed processing according to micro μ instructions read out of control storage device 21. Further, μPC22 monitors the processing execution end of processor 27. Processor 27 interrupts μPC22 right before the processing execution end to let it know the execution end and also outputs the processing result to output data line 30 immediately. In response to the processing execution end of processor 27, μPC22 assigns μ address, assigning a μ instruction, to device 21. Thus, the μ instruction is read out of device 21 and when processor 27 is assigned by this instruction, multiplexer 31 inputs the processing result of processor 27 to μPC22 without using memory bus 24, so that the execution time of instructions is shortened.
COPYRIGHT: (C)1981,JPO&Japio
JP16642579A 1979-12-21 1979-12-21 Data processor Pending JPS5688523A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16642579A JPS5688523A (en) 1979-12-21 1979-12-21 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16642579A JPS5688523A (en) 1979-12-21 1979-12-21 Data processor

Publications (1)

Publication Number Publication Date
JPS5688523A true JPS5688523A (en) 1981-07-18

Family

ID=15831176

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16642579A Pending JPS5688523A (en) 1979-12-21 1979-12-21 Data processor

Country Status (1)

Country Link
JP (1) JPS5688523A (en)

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