JPS5587220A - Interface controller - Google Patents

Interface controller

Info

Publication number
JPS5587220A
JPS5587220A JP16297478A JP16297478A JPS5587220A JP S5587220 A JPS5587220 A JP S5587220A JP 16297478 A JP16297478 A JP 16297478A JP 16297478 A JP16297478 A JP 16297478A JP S5587220 A JPS5587220 A JP S5587220A
Authority
JP
Japan
Prior art keywords
central processor
output
input
process input
wdn
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16297478A
Other languages
Japanese (ja)
Inventor
Fumihiko Takezoe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP16297478A priority Critical patent/JPS5587220A/en
Publication of JPS5587220A publication Critical patent/JPS5587220A/en
Pending legal-status Critical Current

Links

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  • Bus Control (AREA)

Abstract

PURPOSE: To eliminate an influence upon data transfer even if a processing rate would be different, by performing data transfer between a central processor and process input-output unit via a memory.
CONSTITUTION: Output data sent from central processor CPU to process input-output units D1WDN are temporarily stored in the output data region of memory MEM under the control of computer bus interface part INT1. Input data read from process input-output units D1WDN to central processor CPU, on the other hand, are written in the input data region of memory MEM in every constant period under the control of device bus interface part INT2.
COPYRIGHT: (C)1980,JPO&Japio
JP16297478A 1978-12-26 1978-12-26 Interface controller Pending JPS5587220A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16297478A JPS5587220A (en) 1978-12-26 1978-12-26 Interface controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16297478A JPS5587220A (en) 1978-12-26 1978-12-26 Interface controller

Publications (1)

Publication Number Publication Date
JPS5587220A true JPS5587220A (en) 1980-07-01

Family

ID=15764811

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16297478A Pending JPS5587220A (en) 1978-12-26 1978-12-26 Interface controller

Country Status (1)

Country Link
JP (1) JPS5587220A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5840645A (en) * 1981-09-04 1983-03-09 Fujitsu Ltd Input and output control system
JPS61241859A (en) * 1985-04-18 1986-10-28 Sony Corp Data transfering equipment
JPS63244221A (en) * 1987-03-31 1988-10-11 Nec Corp Disk controller
JPH02226454A (en) * 1989-01-13 1990-09-10 Internatl Business Mach Corp <Ibm> Computer system and transfer of data

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5840645A (en) * 1981-09-04 1983-03-09 Fujitsu Ltd Input and output control system
JPS61241859A (en) * 1985-04-18 1986-10-28 Sony Corp Data transfering equipment
JPS63244221A (en) * 1987-03-31 1988-10-11 Nec Corp Disk controller
JPH02226454A (en) * 1989-01-13 1990-09-10 Internatl Business Mach Corp <Ibm> Computer system and transfer of data

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