JPS5528132A - Unit constitution and processing system - Google Patents

Unit constitution and processing system

Info

Publication number
JPS5528132A
JPS5528132A JP9965478A JP9965478A JPS5528132A JP S5528132 A JPS5528132 A JP S5528132A JP 9965478 A JP9965478 A JP 9965478A JP 9965478 A JP9965478 A JP 9965478A JP S5528132 A JPS5528132 A JP S5528132A
Authority
JP
Japan
Prior art keywords
input
output unit
designated
module level
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9965478A
Other languages
Japanese (ja)
Inventor
Ryozo Maeno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP9965478A priority Critical patent/JPS5528132A/en
Publication of JPS5528132A publication Critical patent/JPS5528132A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To increase the freedom at the input and output unit side, by reducing the processing in module level for CPU, by reading out the module level written in the input and output unit designated to the register of the input and output unit repeating the interruption via the bus.
CONSTITUTION: The specified input and output unit is designated among the input and output units 30,31,40,41 from CPU 2, the module level is written in the registor of the multi-input and output controllers 3 and 4 corresponding to the input and output unit designated and also to the registers of all the input and output units. Further, when write-in is returned from the input and output unit other than the input and output units designated to CPU 2, the module level written in the register of the input and output unit designated is read out on the register of the input and output unit returning the interruption through the K bus 1. Thus, the processing in the module level of CPU can be reduced and the freedom in the input and output unit can be increased.
COPYRIGHT: (C)1980,JPO&Japio
JP9965478A 1978-08-16 1978-08-16 Unit constitution and processing system Pending JPS5528132A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9965478A JPS5528132A (en) 1978-08-16 1978-08-16 Unit constitution and processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9965478A JPS5528132A (en) 1978-08-16 1978-08-16 Unit constitution and processing system

Publications (1)

Publication Number Publication Date
JPS5528132A true JPS5528132A (en) 1980-02-28

Family

ID=14253032

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9965478A Pending JPS5528132A (en) 1978-08-16 1978-08-16 Unit constitution and processing system

Country Status (1)

Country Link
JP (1) JPS5528132A (en)

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