JPS54157444A - Memory control system - Google Patents
Memory control systemInfo
- Publication number
- JPS54157444A JPS54157444A JP6575078A JP6575078A JPS54157444A JP S54157444 A JPS54157444 A JP S54157444A JP 6575078 A JP6575078 A JP 6575078A JP 6575078 A JP6575078 A JP 6575078A JP S54157444 A JPS54157444 A JP S54157444A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- word
- writing
- access
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Memory System (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE: To decrease the load of the software when the continuous rading/writing is carried out as well as to increase the velocity of the control process by providing the service control unit to secure a connection between the memory capable of reading N-words at one time and the processor performing the input/output by one word.
CONSTITUTION: The memory which is capable of simultaneous reading and writing for N-words is connected to writing line 3, address line 4 and data line 5 each; and service control circuit 35 performs the input and output with every word. In addition, microorder register 18, selector 11 connected to line 4 plus exclusive reading and writing buffer registers 12 and 13 are provided respectively. Signal 16A designates whether the access for only one word or the continuous access is given from register 18. And if the access is for one word, the wake-up is applied to the memory. While in the case of the continuous access, whether the address is at the boundary of transferred N-words with one cycle of the memory is decided. Based on this result, whether the wake-up is applied to the memory or the transfer is carried out between register 12 and 13 is decided.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6575078A JPS54157444A (en) | 1978-06-02 | 1978-06-02 | Memory control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6575078A JPS54157444A (en) | 1978-06-02 | 1978-06-02 | Memory control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54157444A true JPS54157444A (en) | 1979-12-12 |
Family
ID=13295997
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6575078A Pending JPS54157444A (en) | 1978-06-02 | 1978-06-02 | Memory control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54157444A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63271647A (en) * | 1987-04-30 | 1988-11-09 | Yokogawa Medical Syst Ltd | Memory circuit |
-
1978
- 1978-06-02 JP JP6575078A patent/JPS54157444A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63271647A (en) * | 1987-04-30 | 1988-11-09 | Yokogawa Medical Syst Ltd | Memory circuit |
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