JPS5464939A - Data transfer device - Google Patents

Data transfer device

Info

Publication number
JPS5464939A
JPS5464939A JP13089077A JP13089077A JPS5464939A JP S5464939 A JPS5464939 A JP S5464939A JP 13089077 A JP13089077 A JP 13089077A JP 13089077 A JP13089077 A JP 13089077A JP S5464939 A JPS5464939 A JP S5464939A
Authority
JP
Japan
Prior art keywords
circuit
register
signal
output
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13089077A
Other languages
Japanese (ja)
Other versions
JPS6014382B2 (en
Inventor
Fumiaki Ishibashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP52130890A priority Critical patent/JPS6014382B2/en
Publication of JPS5464939A publication Critical patent/JPS5464939A/en
Publication of JPS6014382B2 publication Critical patent/JPS6014382B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To ensure an easy detection of the plural bit error for the renewal result without causing the great increment of the hardware and reduction of the arithmetic speed by giving a collective check to the results of both the data transfer address and the number of the transfer words.
CONSTITUTION: For the device which performs the data transfer in the order of the rise and fall of the main memory address and based on the designation of the command word, the following units are provided: buffer register 101 to supply the data given from the main memory; and selector circuit 102 to deliver the output of arithmetic circuit 109 and the signal selected by selection address signal 200 to registers 103W105 plus constant register 106. Furthermore, selector circuit 107 which delivers the output of register 105 plus the signal selected to circuit 109 by address signal 202 and 203 is installed, along with selector circuit 108 which delivers the signal selected through input of renewal designation signal 112 to register 105 to circuti 109. Then the value of circuit 108 is added to and subtracted from the value of circuit 107 via circuit 109, and the output is compared between circuit 109 and register 106 through comparator circuit 110. And the error signal 111 is delivered in case no coincidence is obtained through the comparison.
COPYRIGHT: (C)1979,JPO&Japio
JP52130890A 1977-11-02 1977-11-02 data transfer device Expired JPS6014382B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52130890A JPS6014382B2 (en) 1977-11-02 1977-11-02 data transfer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52130890A JPS6014382B2 (en) 1977-11-02 1977-11-02 data transfer device

Publications (2)

Publication Number Publication Date
JPS5464939A true JPS5464939A (en) 1979-05-25
JPS6014382B2 JPS6014382B2 (en) 1985-04-12

Family

ID=15045089

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52130890A Expired JPS6014382B2 (en) 1977-11-02 1977-11-02 data transfer device

Country Status (1)

Country Link
JP (1) JPS6014382B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5844570A (en) * 1981-09-10 1983-03-15 Fujitsu Ltd Fault detecting system for vector processing

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5844570A (en) * 1981-09-10 1983-03-15 Fujitsu Ltd Fault detecting system for vector processing
JPH0226259B2 (en) * 1981-09-10 1990-06-08 Fujitsu Ltd

Also Published As

Publication number Publication date
JPS6014382B2 (en) 1985-04-12

Similar Documents

Publication Publication Date Title
ATE125374T1 (en) CENTRAL PROCESSING UNIT WITH THE CAPABILITY TO SUPPORT COMMANDS OF VARIABLE LENGTH.
JPS56152049A (en) Microprogram control system
JPS54122043A (en) Electronic computer
JPS5464939A (en) Data transfer device
US3618028A (en) Local storage facility
JPS54148439A (en) Information memory unit
JPS55105719A (en) Buffer device
JPS54157444A (en) Memory control system
JPS5525155A (en) Memory access system
JPS55146556A (en) Data collating system
JPS5469921A (en) Processing test system for memory fault
JPS55140949A (en) Information processor
JPS578847A (en) Information processor
JPS5631143A (en) Preventing system for program runaway
JPS5651075A (en) Buffer control system of address conversion
JPS57161928A (en) Variable length buffer device
JPS5452945A (en) Floating decimal point arithmetic control unit
JPS57172582A (en) Cash memory control method
JPS5561847A (en) Check unit for input and output circuit
JPS55139699A (en) Error detection system of memory unit
JPS5697164A (en) Test and set and test and reset system
JPS55162161A (en) Buffer register control system
JPS54111242A (en) Parity bit generation system of partial write control line
JPS5585965A (en) Microprogram branch system
JPS573152A (en) Information processing device