JPS5469921A - Processing test system for memory fault - Google Patents

Processing test system for memory fault

Info

Publication number
JPS5469921A
JPS5469921A JP13666977A JP13666977A JPS5469921A JP S5469921 A JPS5469921 A JP S5469921A JP 13666977 A JP13666977 A JP 13666977A JP 13666977 A JP13666977 A JP 13666977A JP S5469921 A JPS5469921 A JP S5469921A
Authority
JP
Japan
Prior art keywords
fault
memory
processor
circuit
memory unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13666977A
Other languages
Japanese (ja)
Inventor
Kazufumi Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13666977A priority Critical patent/JPS5469921A/en
Publication of JPS5469921A publication Critical patent/JPS5469921A/en
Pending legal-status Critical Current

Links

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  • Techniques For Improving Reliability Of Storages (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To make it possible to test a function of processing memory fault by artificially generating a memory fault in any address of the memory unit without causing artificially a fault in the memory unit in itself.
CONSTITUTION: In an artificial fault generation mode, if coincidence detection signal 231 is sent out from the main-memory access address coincidence circuit which is one of maintenance functions of a processor, the output of AND circuit 43 becomes "1" since artificial fault generation mode control flip-flop 41 has been set, exclusive-OR circuit 44' inverts some of write data such as a check bit or all bits and the data are written to memory unit 1. Consequently, main memory 1 generates fault detection signal 101, which is fetched in fault processor 9 for the purpose of setting fault flip-flop 19', so that the memory fault processing function of the processor will be started.
COPYRIGHT: (C)1979,JPO&Japio
JP13666977A 1977-11-16 1977-11-16 Processing test system for memory fault Pending JPS5469921A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13666977A JPS5469921A (en) 1977-11-16 1977-11-16 Processing test system for memory fault

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13666977A JPS5469921A (en) 1977-11-16 1977-11-16 Processing test system for memory fault

Publications (1)

Publication Number Publication Date
JPS5469921A true JPS5469921A (en) 1979-06-05

Family

ID=15180709

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13666977A Pending JPS5469921A (en) 1977-11-16 1977-11-16 Processing test system for memory fault

Country Status (1)

Country Link
JP (1) JPS5469921A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5935238A (en) * 1982-08-20 1984-02-25 Nec Corp Information processor
JPS60239838A (en) * 1984-05-15 1985-11-28 Nec Corp False fault generator
JPS6292042A (en) * 1985-10-18 1987-04-27 Nec Corp Memory device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5935238A (en) * 1982-08-20 1984-02-25 Nec Corp Information processor
JPS60239838A (en) * 1984-05-15 1985-11-28 Nec Corp False fault generator
JPS6292042A (en) * 1985-10-18 1987-04-27 Nec Corp Memory device
JPH0535455B2 (en) * 1985-10-18 1993-05-26 Nippon Electric Co

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