JPS5587397A - Memory device - Google Patents

Memory device

Info

Publication number
JPS5587397A
JPS5587397A JP16042178A JP16042178A JPS5587397A JP S5587397 A JPS5587397 A JP S5587397A JP 16042178 A JP16042178 A JP 16042178A JP 16042178 A JP16042178 A JP 16042178A JP S5587397 A JPS5587397 A JP S5587397A
Authority
JP
Japan
Prior art keywords
data
check bit
register
time
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16042178A
Other languages
Japanese (ja)
Inventor
Noriyuki Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP16042178A priority Critical patent/JPS5587397A/en
Publication of JPS5587397A publication Critical patent/JPS5587397A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To eliminate the delay time caused by generation of the check bit and thus to reduce the writing cycle time by preventing the time to generate the check bit from being added to the writing cycle time of the memory device.
CONSTITUTION: When the writing address and the data are transferred to registers 3 and 4 respectively from the CPU, the data is transferred to generator 5 from register 4 to generate the check bit corresponding to the data. At the same time, the data is written to the fixed address of memory part 1, and the check bit at the preceding data writing time is written into memory part 2 via register 6. And with application of the reading address from the CPU, both the data and the check bit are read out of each memory part to be supplied to error check circuit 11 and register 13. And thus the error, if any, is corrected and then transferred to the CPU from register 13.
COPYRIGHT: (C)1980,JPO&Japio
JP16042178A 1978-12-25 1978-12-25 Memory device Pending JPS5587397A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16042178A JPS5587397A (en) 1978-12-25 1978-12-25 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16042178A JPS5587397A (en) 1978-12-25 1978-12-25 Memory device

Publications (1)

Publication Number Publication Date
JPS5587397A true JPS5587397A (en) 1980-07-02

Family

ID=15714554

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16042178A Pending JPS5587397A (en) 1978-12-25 1978-12-25 Memory device

Country Status (1)

Country Link
JP (1) JPS5587397A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5263030A (en) * 1991-02-13 1993-11-16 Digital Equipment Corporation Method and apparatus for encoding data for storage on magnetic tape

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5263030A (en) * 1991-02-13 1993-11-16 Digital Equipment Corporation Method and apparatus for encoding data for storage on magnetic tape

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