JPS556679A - Check system of error control circuit - Google Patents

Check system of error control circuit

Info

Publication number
JPS556679A
JPS556679A JP7958178A JP7958178A JPS556679A JP S556679 A JPS556679 A JP S556679A JP 7958178 A JP7958178 A JP 7958178A JP 7958178 A JP7958178 A JP 7958178A JP S556679 A JPS556679 A JP S556679A
Authority
JP
Japan
Prior art keywords
error
memory
register
generator
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7958178A
Other languages
Japanese (ja)
Inventor
Tomohito Shibata
Toshiaki Ii
Shigeru Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7958178A priority Critical patent/JPS556679A/en
Publication of JPS556679A publication Critical patent/JPS556679A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To simplify a check on a circuit by providing an error generator in a memory unit, by reading out data from a memory address when a start flag is registered in an error control register constituting the error generator and by modifying the read data according to the content of the error data register.
CONSTITUTION: The check system consists of central processor 1, memory 2, common bus 3, error generator 4, error control register 5, error address register 6, error data register 7, bit inverter 8, DMA control part 9, parity checking-generator 10, etc. In the constitution, unit 1 write desired data to registers 6 and 7 after the data are written to memory 2 and a start flag is set in register 7 to operate generator 4, thereby storing addresses in memory 2 in generator 4. Next, EOR with register 7 is extracted and stored at the original address of memory 2 and data with its parity bit disagreeing with the information bit is written to memory 2.
COPYRIGHT: (C)1980,JPO&Japio
JP7958178A 1978-06-30 1978-06-30 Check system of error control circuit Pending JPS556679A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7958178A JPS556679A (en) 1978-06-30 1978-06-30 Check system of error control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7958178A JPS556679A (en) 1978-06-30 1978-06-30 Check system of error control circuit

Publications (1)

Publication Number Publication Date
JPS556679A true JPS556679A (en) 1980-01-18

Family

ID=13693942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7958178A Pending JPS556679A (en) 1978-06-30 1978-06-30 Check system of error control circuit

Country Status (1)

Country Link
JP (1) JPS556679A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56144985U (en) * 1980-03-28 1981-10-31

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56144985U (en) * 1980-03-28 1981-10-31

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