JPS55146551A - Information processing unit - Google Patents

Information processing unit

Info

Publication number
JPS55146551A
JPS55146551A JP5245779A JP5245779A JPS55146551A JP S55146551 A JPS55146551 A JP S55146551A JP 5245779 A JP5245779 A JP 5245779A JP 5245779 A JP5245779 A JP 5245779A JP S55146551 A JPS55146551 A JP S55146551A
Authority
JP
Japan
Prior art keywords
register
address
write
change
cache memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5245779A
Other languages
Japanese (ja)
Inventor
Koemon Nigo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5245779A priority Critical patent/JPS55146551A/en
Publication of JPS55146551A publication Critical patent/JPS55146551A/en
Pending legal-status Critical Current

Links

Landscapes

  • Retry When Errors Occur (AREA)

Abstract

PURPOSE: To obtain an information processing unit which is able to carry out a retrial easily, by holding the address until a write error check is finished, in case of write processing to a main memory.
CONSTITUTION: At the time of write processing, an address 50 is provided not only to a cache memory 3 which operates as a buffer, through a change-over circuit 1, but also to a register 7 and a main memory 9 through an address register 5. As a result of the foregoing, a control circuit 8 writes a data from a bus 53 in the main memory 9 through a change-over circuit 2, the cache memory 3, a change-over circuit 4 and a data register 6. The register 7 holds a write address until the write processing is finished, the control circuit 8 sends the address which has been held in the register 7, through the change-over circuit 1 to the cache memory 3 and the address register 5, when a write error information is received from a processor, and the rewrite processing is executed by reading out a data in the cache memory 3.
COPYRIGHT: (C)1980,JPO&Japio
JP5245779A 1979-05-01 1979-05-01 Information processing unit Pending JPS55146551A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5245779A JPS55146551A (en) 1979-05-01 1979-05-01 Information processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5245779A JPS55146551A (en) 1979-05-01 1979-05-01 Information processing unit

Publications (1)

Publication Number Publication Date
JPS55146551A true JPS55146551A (en) 1980-11-14

Family

ID=12915239

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5245779A Pending JPS55146551A (en) 1979-05-01 1979-05-01 Information processing unit

Country Status (1)

Country Link
JP (1) JPS55146551A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63206846A (en) * 1987-02-24 1988-08-26 Fujitsu Ltd Memory access rerun system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63206846A (en) * 1987-02-24 1988-08-26 Fujitsu Ltd Memory access rerun system

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