JPS6410389A - Data enlarging system - Google Patents

Data enlarging system

Info

Publication number
JPS6410389A
JPS6410389A JP62166363A JP16636387A JPS6410389A JP S6410389 A JPS6410389 A JP S6410389A JP 62166363 A JP62166363 A JP 62166363A JP 16636387 A JP16636387 A JP 16636387A JP S6410389 A JPS6410389 A JP S6410389A
Authority
JP
Japan
Prior art keywords
enlarging
address
image data
processor
designated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62166363A
Other languages
Japanese (ja)
Inventor
Wataru Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62166363A priority Critical patent/JPS6410389A/en
Publication of JPS6410389A publication Critical patent/JPS6410389A/en
Pending legal-status Critical Current

Links

Landscapes

  • Image Processing (AREA)
  • Memory System (AREA)

Abstract

PURPOSE:To execute the highly speedy enlarging processing of image data by executing the transferring of the image data with a processor when the image data are enlarged. CONSTITUTION:An address shift circuit 13 designates an address at a time image data are read from a memory 11 in correspondence to an enlarging value designated by an enlarging designating circuit 12. A data enlarging circuit 14, in correspondence to the enlarging value designated by the enlarging designating circuit 12, fetches a designated bit number from the low order bit of an address sent by a processor 10 and decodes them. With an address designated by the address shift circuit 13, the image data are enlarged from the memory 11 in correspondence to the designated enlarging value, read and sent to the processor 10. The address shift circuit 13 sends this address sent by the processor 10 to the memory 11 and the address is written in the memory 11. Accordingly, the processor only executes the reading and writing of the image data and it is not necessary to execute, as in the past, an enlarging processing by the program.
JP62166363A 1987-07-03 1987-07-03 Data enlarging system Pending JPS6410389A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62166363A JPS6410389A (en) 1987-07-03 1987-07-03 Data enlarging system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62166363A JPS6410389A (en) 1987-07-03 1987-07-03 Data enlarging system

Publications (1)

Publication Number Publication Date
JPS6410389A true JPS6410389A (en) 1989-01-13

Family

ID=15830008

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62166363A Pending JPS6410389A (en) 1987-07-03 1987-07-03 Data enlarging system

Country Status (1)

Country Link
JP (1) JPS6410389A (en)

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