JPS5543680A - Address designation system - Google Patents

Address designation system

Info

Publication number
JPS5543680A
JPS5543680A JP11714378A JP11714378A JPS5543680A JP S5543680 A JPS5543680 A JP S5543680A JP 11714378 A JP11714378 A JP 11714378A JP 11714378 A JP11714378 A JP 11714378A JP S5543680 A JPS5543680 A JP S5543680A
Authority
JP
Japan
Prior art keywords
contents
registers
buffer
register
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11714378A
Other languages
Japanese (ja)
Other versions
JPS623462B2 (en
Inventor
Junichi Iwasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11714378A priority Critical patent/JPS5543680A/en
Publication of JPS5543680A publication Critical patent/JPS5543680A/en
Publication of JPS623462B2 publication Critical patent/JPS623462B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To reduce the program quantity by dividing the general-purpose register which stores the operand and address modifying data for the arithmetic object into plural patial registers featuring a short bit number each and then performing the alteration for the register contents with a small amount of the order.
CONSTITUTION: The address designation is given to memory 11 according to the contents of data buffer 13, and the contents of buffer 13 is written into the address position designated by the contents and then read out from memory 11 to be stored in buffer 13. At the same time, the order in the contents of buffer 13 is set to order register 14, and the contents of register 14 is decoded via decoder 15. Then the contents of buffer 13 is applied to arithmetic registers 17 and 18 as well as to arithmetic circuit 19 and then supplied to general-purpose registers 21 and 22 after calculation. Registers 21 and 22 are divided into plural partial registers featuring the bit number same as or shorter than the data length of circuit 19. And the designation of different positions is secured for registers 21 and 22 according to the contents of the address.
COPYRIGHT: (C)1980,JPO&Japio
JP11714378A 1978-09-22 1978-09-22 Address designation system Granted JPS5543680A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11714378A JPS5543680A (en) 1978-09-22 1978-09-22 Address designation system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11714378A JPS5543680A (en) 1978-09-22 1978-09-22 Address designation system

Publications (2)

Publication Number Publication Date
JPS5543680A true JPS5543680A (en) 1980-03-27
JPS623462B2 JPS623462B2 (en) 1987-01-24

Family

ID=14704514

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11714378A Granted JPS5543680A (en) 1978-09-22 1978-09-22 Address designation system

Country Status (1)

Country Link
JP (1) JPS5543680A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE40498E1 (en) 1993-05-27 2008-09-09 Matsushita Electric Industrial Co., Ltd. Variable address length compiler and processor improved in address management

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0427830Y2 (en) * 1986-04-16 1992-07-03

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE40498E1 (en) 1993-05-27 2008-09-09 Matsushita Electric Industrial Co., Ltd. Variable address length compiler and processor improved in address management
USRE41959E1 (en) 1993-05-27 2010-11-23 Panasonic Corporation Variable address length compiler and processor improved in address management

Also Published As

Publication number Publication date
JPS623462B2 (en) 1987-01-24

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