JPS54146546A - Data processor - Google Patents

Data processor

Info

Publication number
JPS54146546A
JPS54146546A JP5520178A JP5520178A JPS54146546A JP S54146546 A JPS54146546 A JP S54146546A JP 5520178 A JP5520178 A JP 5520178A JP 5520178 A JP5520178 A JP 5520178A JP S54146546 A JPS54146546 A JP S54146546A
Authority
JP
Japan
Prior art keywords
order
register
store
registers
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5520178A
Other languages
Japanese (ja)
Inventor
Tsukasa Furuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5520178A priority Critical patent/JPS54146546A/en
Publication of JPS54146546A publication Critical patent/JPS54146546A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To enable rewriting of the order by handling the order register in the same level as other general-purpose registers and thus to ensure the process for the versatile data with the minimum quantity of both the hardware and the program.
CONSTITUTION: The following units are provided: program memory 1 to store the program comprising plural number of orders; address register 7 to store the address which designated the order storage unit within memory 1; plus order registers 3 and 4 to store the orders read out from memory 1. In addition, external register 6 is provided to store the order given from outside, along with decoding control circuit 2 which delivers control signal 17 after decoding the order given from order register 3 plus selection circuit 8 which selects the output with the output of registers 3W7 and signal 17 of circuit 2 used as the input and then supplies the output to arithmetic circuit 9. Thus, the contents of register 6 is stored in registers 3, 4 and 5 based on signal 17 decoded through circuit 2.
COPYRIGHT: (C)1979,JPO&Japio
JP5520178A 1978-05-09 1978-05-09 Data processor Pending JPS54146546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5520178A JPS54146546A (en) 1978-05-09 1978-05-09 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5520178A JPS54146546A (en) 1978-05-09 1978-05-09 Data processor

Publications (1)

Publication Number Publication Date
JPS54146546A true JPS54146546A (en) 1979-11-15

Family

ID=12992053

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5520178A Pending JPS54146546A (en) 1978-05-09 1978-05-09 Data processor

Country Status (1)

Country Link
JP (1) JPS54146546A (en)

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