JPS54156434A - Jump system between pages - Google Patents

Jump system between pages

Info

Publication number
JPS54156434A
JPS54156434A JP6595878A JP6595878A JPS54156434A JP S54156434 A JPS54156434 A JP S54156434A JP 6595878 A JP6595878 A JP 6595878A JP 6595878 A JP6595878 A JP 6595878A JP S54156434 A JPS54156434 A JP S54156434A
Authority
JP
Japan
Prior art keywords
register
timing
delay circuit
executed
page
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6595878A
Other languages
Japanese (ja)
Inventor
Tomiji Hara
Toshiro Mizuno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP6595878A priority Critical patent/JPS54156434A/en
Publication of JPS54156434A publication Critical patent/JPS54156434A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To enable to extend the address space storing the program, by providing the register and delay circuit designating the page to be jumped between the microprocessor and the memory.
CONSTITUTION: The microprocessor μP1 outputs the data to be set to the location page register 3. When the decoder 5 receives this set timing, it delivers the data latch timing to the buffer register 4 and also starts the delay circuit 6. In this timing, the register 4 latches the address to be set to the register 3. Next, the μP1 executes the jump instruction. The delay circuit 6 delays the signal outputted from the decoder 5 until the jump instruction is executed, to deliver the signal writing in the content of the register 4 to the register 3. With the timing of this signal, the content of the register 3 is rewritten in the page address storing the program next executed. Thus, the jump between pages can be executed.
COPYRIGHT: (C)1979,JPO&Japio
JP6595878A 1978-05-30 1978-05-30 Jump system between pages Pending JPS54156434A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6595878A JPS54156434A (en) 1978-05-30 1978-05-30 Jump system between pages

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6595878A JPS54156434A (en) 1978-05-30 1978-05-30 Jump system between pages

Publications (1)

Publication Number Publication Date
JPS54156434A true JPS54156434A (en) 1979-12-10

Family

ID=13301994

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6595878A Pending JPS54156434A (en) 1978-05-30 1978-05-30 Jump system between pages

Country Status (1)

Country Link
JP (1) JPS54156434A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58123142A (en) * 1982-01-19 1983-07-22 Nec Corp Information processor
JPH01204147A (en) * 1988-02-09 1989-08-16 Toshiba Corp Address qualifying circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58123142A (en) * 1982-01-19 1983-07-22 Nec Corp Information processor
JPH01204147A (en) * 1988-02-09 1989-08-16 Toshiba Corp Address qualifying circuit

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