JPS5452936A - Memroy processor - Google Patents
Memroy processorInfo
- Publication number
- JPS5452936A JPS5452936A JP11959877A JP11959877A JPS5452936A JP S5452936 A JPS5452936 A JP S5452936A JP 11959877 A JP11959877 A JP 11959877A JP 11959877 A JP11959877 A JP 11959877A JP S5452936 A JPS5452936 A JP S5452936A
- Authority
- JP
- Japan
- Prior art keywords
- order
- nop
- circuit
- signal
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE: To correct the all data of the memory when the initial program loader is started by writing the data of correct parity featuring the same code as the NOP order into the memory storing the program with every advance of the program counter.
CONSTITUTION: Control circuit 63 transmits signal T indicating the execution cycle. OR circuit 73 and 74 set FF75 and delivers the NOP signal. Thus, the NOP order is sent to data bus 1 and then set to order register 61. The NOP order is then decoded through decoder 62 to be supplied to control circuit 63. In the execution cycle of the order, signal T is supplied to AND circuit 78. As a result, write signal W is delivered from circuit 78, and the code of the NOP order on bus 1 is written to the zero address of the memory
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11959877A JPS5452936A (en) | 1977-10-04 | 1977-10-04 | Memroy processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11959877A JPS5452936A (en) | 1977-10-04 | 1977-10-04 | Memroy processor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5452936A true JPS5452936A (en) | 1979-04-25 |
JPS5719450B2 JPS5719450B2 (en) | 1982-04-22 |
Family
ID=14765343
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11959877A Granted JPS5452936A (en) | 1977-10-04 | 1977-10-04 | Memroy processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5452936A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55165336U (en) * | 1979-05-11 | 1980-11-27 | ||
JPS57139988U (en) * | 1981-02-27 | 1982-09-01 | ||
JPS585843A (en) * | 1981-07-01 | 1983-01-13 | Mitsubishi Electric Corp | Optional address starting device |
JPS5870366A (en) * | 1981-10-22 | 1983-04-26 | Nec Corp | Memory controlling circuit for microprocessor |
-
1977
- 1977-10-04 JP JP11959877A patent/JPS5452936A/en active Granted
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55165336U (en) * | 1979-05-11 | 1980-11-27 | ||
JPS57139988U (en) * | 1981-02-27 | 1982-09-01 | ||
JPS6114074Y2 (en) * | 1981-02-27 | 1986-05-01 | ||
JPS585843A (en) * | 1981-07-01 | 1983-01-13 | Mitsubishi Electric Corp | Optional address starting device |
JPS5870366A (en) * | 1981-10-22 | 1983-04-26 | Nec Corp | Memory controlling circuit for microprocessor |
Also Published As
Publication number | Publication date |
---|---|
JPS5719450B2 (en) | 1982-04-22 |
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