JPS5510659A - Data processor - Google Patents

Data processor

Info

Publication number
JPS5510659A
JPS5510659A JP8320778A JP8320778A JPS5510659A JP S5510659 A JPS5510659 A JP S5510659A JP 8320778 A JP8320778 A JP 8320778A JP 8320778 A JP8320778 A JP 8320778A JP S5510659 A JPS5510659 A JP S5510659A
Authority
JP
Japan
Prior art keywords
instruction
content
execution
decided whether
specific condition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8320778A
Other languages
Japanese (ja)
Inventor
Katsuyuki Shimokawa
Itaru Tanimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8320778A priority Critical patent/JPS5510659A/en
Priority to US06/054,577 priority patent/US4298933A/en
Priority to AU48723/79A priority patent/AU528284B2/en
Priority to DE2927481A priority patent/DE2927481C2/en
Publication of JPS5510659A publication Critical patent/JPS5510659A/en
Pending legal-status Critical Current

Links

Landscapes

  • Devices For Executing Special Programs (AREA)
  • Control By Computers (AREA)

Abstract

PURPOSE: To shorten the mean execution time for instrucons by disabling one instruction or following instructions for execution under a specific condition.
CONSTITUTION: An instruction is read out from the memory unit to the instruction register and it is decided whether the content of counter 32 is "0" or not, namely, whether there are parenthesises; in case of the AND instruction, it is decided whether or not the content of bit accumulator 30 is "0" and in case of the OR instruction, it is decided whether or not the content of bit accumulator 30 is "1". Then, when this specific condition fails, address calculation operation fetch and instruction execution are carried out and when coming into existence, operations from the address calculation to instruction execution are omitted.
COPYRIGHT: (C)1980,JPO&Japio
JP8320778A 1978-07-08 1978-07-08 Data processor Pending JPS5510659A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP8320778A JPS5510659A (en) 1978-07-08 1978-07-08 Data processor
US06/054,577 US4298933A (en) 1978-07-08 1979-07-03 Data-processing device including means to suppress the execution of unnecessary instructions
AU48723/79A AU528284B2 (en) 1978-07-08 1979-07-06 Shortening execution time of data processor
DE2927481A DE2927481C2 (en) 1978-07-08 1979-07-06 Data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8320778A JPS5510659A (en) 1978-07-08 1978-07-08 Data processor

Publications (1)

Publication Number Publication Date
JPS5510659A true JPS5510659A (en) 1980-01-25

Family

ID=13795870

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8320778A Pending JPS5510659A (en) 1978-07-08 1978-07-08 Data processor

Country Status (1)

Country Link
JP (1) JPS5510659A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58166443A (en) * 1982-03-27 1983-10-01 Fujitsu Ltd Logical arithmetic control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58166443A (en) * 1982-03-27 1983-10-01 Fujitsu Ltd Logical arithmetic control system
JPH0117175B2 (en) * 1982-03-27 1989-03-29 Fujitsu Ltd

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