JPS5587362A - Buffer memory control system - Google Patents

Buffer memory control system

Info

Publication number
JPS5587362A
JPS5587362A JP15901378A JP15901378A JPS5587362A JP S5587362 A JPS5587362 A JP S5587362A JP 15901378 A JP15901378 A JP 15901378A JP 15901378 A JP15901378 A JP 15901378A JP S5587362 A JPS5587362 A JP S5587362A
Authority
JP
Japan
Prior art keywords
buffer
operand
store
data
instruction fetch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15901378A
Other languages
Japanese (ja)
Inventor
Hirosada Tone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15901378A priority Critical patent/JPS5587362A/en
Publication of JPS5587362A publication Critical patent/JPS5587362A/en
Pending legal-status Critical Current

Links

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  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To enhance the data process performance for the buffer memory device of the data processor of pipe line system by securing the independent separation between the instruction fetch buffer and the operand buffer and also securing execution of the operand store for both buffers.
CONSTITUTION: Operand buffer 3 and instruction fetch buffer 4 are separate from each other, and given the access by address registers 1 and 2 independently. While at the operand store time, the operand address is applied to registers 1 and 2, and the operand data set to store data register 5 is stored in buffer 3. At the same time, the operand data is stored in buffer 4 only in case the store address block exists within buffer 4. And in case the subsequent order is rewritten by the store instruction, the simultaneous buffer access is possible to both the instruction fetch and the operand fetch with prevention of the fact that the unnecessary data remains with no renewal.
COPYRIGHT: (C)1980,JPO&Japio
JP15901378A 1978-12-22 1978-12-22 Buffer memory control system Pending JPS5587362A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15901378A JPS5587362A (en) 1978-12-22 1978-12-22 Buffer memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15901378A JPS5587362A (en) 1978-12-22 1978-12-22 Buffer memory control system

Publications (1)

Publication Number Publication Date
JPS5587362A true JPS5587362A (en) 1980-07-02

Family

ID=15684329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15901378A Pending JPS5587362A (en) 1978-12-22 1978-12-22 Buffer memory control system

Country Status (1)

Country Link
JP (1) JPS5587362A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6027966A (en) * 1983-07-27 1985-02-13 Hitachi Ltd Buffer storage control system
JPS63177238A (en) * 1986-10-17 1988-07-21 アムダール コーポレーション Data processor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6027966A (en) * 1983-07-27 1985-02-13 Hitachi Ltd Buffer storage control system
JPH059818B2 (en) * 1983-07-27 1993-02-08 Hitachi Ltd
JPS63177238A (en) * 1986-10-17 1988-07-21 アムダール コーポレーション Data processor

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