JPS5654558A - Write control system for main memory unit - Google Patents

Write control system for main memory unit

Info

Publication number
JPS5654558A
JPS5654558A JP13012279A JP13012279A JPS5654558A JP S5654558 A JPS5654558 A JP S5654558A JP 13012279 A JP13012279 A JP 13012279A JP 13012279 A JP13012279 A JP 13012279A JP S5654558 A JPS5654558 A JP S5654558A
Authority
JP
Japan
Prior art keywords
write
requests
access
main memory
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13012279A
Other languages
Japanese (ja)
Other versions
JPS5941215B2 (en
Inventor
Takashi Chiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP54130122A priority Critical patent/JPS5941215B2/en
Publication of JPS5654558A publication Critical patent/JPS5654558A/en
Publication of JPS5941215B2 publication Critical patent/JPS5941215B2/en
Expired legal-status Critical Current

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  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To finish write operation through single operation by detecting the generation of a continuous write request for the same access unit of a memory unit and by simultaneously merging the following write request data.
CONSTITUTION: When requests from CPUs 1-1 and 1-2 and CHPs 2-1 and 2-2 as processors are written in main memory units 3-1 and 3-2, requests are stored in port parts 5-1W 5-4 temporarily and various information including this stored access address information and write data is inputted to shift register 9 and held there during an access run. Address information outputted from this register 9 is compared by comparing circuit 20 with access addresses held in port parts 5-1W5-4. When circuit 20 detects the generation of continuous write requests for the same single area of units 3-1 and 3-2, the following write request data are merged by the merging circuit with write processing data before the execution, so that the processing may be completed through the single write operation.
COPYRIGHT: (C)1981,JPO&Japio
JP54130122A 1979-10-09 1979-10-09 Main memory write control method Expired JPS5941215B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54130122A JPS5941215B2 (en) 1979-10-09 1979-10-09 Main memory write control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54130122A JPS5941215B2 (en) 1979-10-09 1979-10-09 Main memory write control method

Publications (2)

Publication Number Publication Date
JPS5654558A true JPS5654558A (en) 1981-05-14
JPS5941215B2 JPS5941215B2 (en) 1984-10-05

Family

ID=15026466

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54130122A Expired JPS5941215B2 (en) 1979-10-09 1979-10-09 Main memory write control method

Country Status (1)

Country Link
JP (1) JPS5941215B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60136874A (en) * 1983-12-26 1985-07-20 Hitachi Ltd Vector processor
JPS6238953A (en) * 1985-08-14 1987-02-19 Fujitsu Ltd Main storage device for compression of partial write access
JPS6386044A (en) * 1986-09-30 1988-04-16 Fujitsu Ltd Merging system for store buffer
JPS63129437A (en) * 1986-11-19 1988-06-01 Fujitsu Ltd Partial write control system
US20070220197A1 (en) * 2005-01-31 2007-09-20 M-Systems Flash Disk Pioneers, Ltd. Method of managing copy operations in flash memories
US11321354B2 (en) * 2019-10-01 2022-05-03 Huawei Technologies Co., Ltd. System, computing node and method for processing write requests

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6130619U (en) * 1984-07-27 1986-02-24 株式会社 ダイヤパツケ−ジ packaging container
WO1992005489A1 (en) * 1990-09-18 1992-04-02 Fujitsu Limited Method of nonsynchronous access to shared memory

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60136874A (en) * 1983-12-26 1985-07-20 Hitachi Ltd Vector processor
JPH0414384B2 (en) * 1983-12-26 1992-03-12 Hitachi Ltd
JPS6238953A (en) * 1985-08-14 1987-02-19 Fujitsu Ltd Main storage device for compression of partial write access
JPS6386044A (en) * 1986-09-30 1988-04-16 Fujitsu Ltd Merging system for store buffer
JPS63129437A (en) * 1986-11-19 1988-06-01 Fujitsu Ltd Partial write control system
US20070220197A1 (en) * 2005-01-31 2007-09-20 M-Systems Flash Disk Pioneers, Ltd. Method of managing copy operations in flash memories
US8341371B2 (en) * 2005-01-31 2012-12-25 Sandisk Il Ltd Method of managing copy operations in flash memories
US11321354B2 (en) * 2019-10-01 2022-05-03 Huawei Technologies Co., Ltd. System, computing node and method for processing write requests

Also Published As

Publication number Publication date
JPS5941215B2 (en) 1984-10-05

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