JPS60136874A - Vector processor - Google Patents

Abstract

PURPOSE:To execute a vector fetching/storing instruction at high speed by gathering together requests for plual vector elements which are processed by a data transmission circuit to one request, and transmitting it to a storage controller. CONSTITUTION:An output of a prerequest formation circuit 27-1 is transmitted to a request and additional information formation circuit 27-4, and the formed request and the fetch request additional information are transmitted to passes 15-1 and 15-2 respectively. The request address which is formed by a request address calculation circuit 27-3 is transmitted to a pass 15-3 in synchonization with these. A VR writing control circuit 27-14 receives the fetch request additional information, when it is a request which complexes two 4-byte fetches, forms an advance signal two times, and transmits the signal to a pass 18-1. Then, the control circuit 27-14 transmits the mask value which corresponds to two-time advance signals to a pass 18-2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a vector processing device, and in particular to a vector register unit including a main memory (hereinafter referred to as a storage device) and a plurality of vector registers (hereinafter referred to as a VR). The present invention relates to a vector processing device suitable for high-speed data transfer between VRUs (hereinafter referred to as VRUs).

[Background of the invention]

FIG. 1 shows an example of the configuration of a vector processing @ device. This example is commonly used in the one-shot of the conventional example and the embodiment of the present invention.

In FIG. 1, the MSl consists of eight independently operable storage devices (hereinafter referred to as boats), and the valley boats further include four
It consists of several independently operable storage devices (hereinafter referred to as banks). Each boat has a storage controller (hereinafter referred to as SC) 2
There are eight 8-byte wide MSiA output/write paths 7 to 14 between the MSiA and the MSiA. When an 8-byte vector fetch instruction is activated, the data transfer circuit (hereinafter referred to as DTC) 3 transfers M
The address of each element of the vector data arranged on Sl is calculated in sequence, and a request is sent to SC4 using one of the two fetch paths 15 to 16, for example 15. The SC4 sends the received request to the corresponding boat (for example, boat 0) to the MSI output/write address (for example, the cell corresponding to boat 0). output/write)
transfer using kusufutosuru). Boat 0 is SC2
According to the address in the boat sent from
After a bank busy time (for example, 7 cycles) corresponding to an 8-byte fetch, the fetched data is transferred to SC,2 using MSS output/write path 7. The SC2 transfers the received fetch data to the DTC3 using the fetch path 15.

DTC5 sequentially receives the 8-byte data as is.
VR using vector register (VR) write path 18
By transferring the 8-byte data received by VRU2 to U2 and writing the 8-byte data received by VRU2 into an appropriate element symbol (■) of the symbol specified at the time of instruction activation, the fetch request processing for one element is completed. By sequentially repeating such processing as many times as the number of vector elements (also called vector length), execution of one 8-byte vector fetch instruction is completed.

An 8-byte vector fetch instruction can be executed in the same manner using the fetch path 16 and the VR write path 19.

When the 8-byte vector store instruction is activated, VRU2
reads the 8-byte data in the order of the master number from the VR of the master number specified at the time of command activation, using the VR read path 20, and reads it to the DT.
Send C3K. DTC3 C, V-RU2 C6 Sequentially calculates the MS address where the sequentially sent vector data should be stored, and transfers it to SC4 as an 8-byte store request using store path 17 along with the store data received from VRU2. do. As in the case of fetish request processing, the SC4 receives the received request according to its address and sends it to the corresponding port of the MSI on the hoard-enabled MS read/write path (e.g., port.

7). At boat 0, 8-byte data is written according to the address within the boat sent from SC2, thereby completing the store request processing for one element. By sequentially repeating such processing for the number of vector elements, execution of one 8-byte vector store instruction is completed.

In the DTC3, address calculation is performed in units of 1 byte, and the lower 3 bits are cut off to generate a request address to be sent to the SC. In the 4-byte vector 7 etch/store instruction, the above truncated 3
The most significant 1 bit of the bits is added to the request as additional information for specifying whether it is the upper 4 bytes or the upper 4 bytes of the corresponding request. In the 4-byte vector fetch instruction, the upper 4 bytes or lower 4 bytes are extracted from the 8-byte 7-fetch data transferred from SC4 to DTC3 using the above addition 1'VW and sent to U2. The busy time is 7 cycles as in the case of the 8-byte vector fetch instruction.

In the 4-byte vector store instruction, in order to create an ECC code provided in 8-byte units, 8-byte data is first read out according to the request address, and the data is read from the VRU 2 to the VR indulgence path 20, DTC 5, store path 417,
Using the above additional information, the 4-byte store data sent via SC4 and Ms read/write path 7 is
Half is replaced and the resulting 8-byte data is written into the MS l, jl area specified by the request address. Therefore, while the bank busy time for an 8-byte vector store instruction is 7 cycles, the bank busy time for a 4-byte vector store instruction is about twice as long, for example, 15 cycles.

In a conventional vector processing device, when executing an 8-byte vector store instruction with a mask, the mask value is requested as additional information in DT(j) in order to suppress the physical store whose mask 1 corresponds to the element of Ioo. Add to.

The MSl checks the additional information and suppresses the store operation. According to this method, due to the store operation not being executed,
The bank is busy for 7 cycles and is filled in at SC4.

Next, consider a case where a conventional vector processing device executes a 4-byte vector fetch/store instruction with consecutive addresses. Execution of a general 4-byte vector fetch/store instruction has already been described. The request address is calculated at DT (j), but in most cases, this address is determined by adding the inter-element interval (hereinafter referred to as VLR) to the start address of the vector (hereinafter referred to as ■mount) by j@. .When LR is ±4, each element of the vector is consecutively arranged on MS.

Such a case is called a 4-byte vector fetch/store instruction with consecutive addresses.

For example, the bottom 8 bits of starvation are 0, and V=R” 40
4-byte vector A-(A(o), A(1),
=・-A(n)) "When executing the fetch instruction LA, A(0) and A(1) are stored in the first half and second half of the bank 008 byte of MSIS water table 0. , there is a bank conflict and A( from SC4 to MSl
1) Fetch request &';! , A(0) will be sent 7 cycles after the fetch request.

The 7-etch request of A(2) is sent in the next cycle of the 7-etch request of A(1), and similarly, bank conflicts occur once every two elements, and the request processing of this instruction is delayed. Throughput ignores bank conflicts with other concurrently executing fetch/store instructions.
The average is 2 requests/8 cycles, and the processing throughput for 4-byte vector fetch instructions, 8-byte vector fetch instructions, etc. when addresses are not consecutive is approximately 1
/4. This situation is shown in the time chart of FIG.

+1ffJ 4fj K L-C1VAR (7) Lower 8
Bit is 101 Teari, VJ-4 4-byte pect k
C= (C(o), C(1), ・------
When executing the instruction ST C to store in C(n) ), as shown in FIG. 4, the request processing is 2 requests/16 cycles, and the throughput is approximately 1/8.

Figure 2 shows the 8-byte vector A-(A(0, A(1)
...-= A(n) ), also an 8-byte pect #
B - (B(ol, B(1)...B(n
)), respectively, and the same 8-byte vectors C-(C(0), C(1
), . . . C(n)) are executed simultaneously to achieve the highest throughput.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a vector processing device that can execute vector fetch/store instructions at high speed by processing multiple requests at once, avoiding contention in memory banks of a main storage device. It is in.

[Summary of the invention]

In the present invention, a main memory device, a plurality of vector registers for storing vector rotors, and n! A data transfer circuit that controls data transfer between the storage device and the vector register, and a main memory access from the data transfer circuit to the main memory device, and in response to a fetch request, # Ij Transfers the fetish data read from the MC main memory to the data transfer circuit, and in response to a store request, transfers the store data received from the data transfer circuit to the main memory. Refrain [
In the vector processing device, requests for a plurality of vector elements to be processed by the data transfer circuit are combined into one and transferred to the storage control device, and The device processes the request as a single request, and in response to a fetch request, the data transfer circuit divides the fetch data into data corresponding to multiple requests and sequentially transfers them to the vector register. In contrast, in the data transfer circuit, a plurality of store data are transferred from the previous vector register.
1 request and transfer it to the storage control device,
It is characterized in that the information is written to the main memory at one time.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

As described in the explanation of conventional capabilities, the DTC3 can simultaneously process two vector fetch instructions and one vector store instruction. Internal structure of DTC3 and SC4
, and VRU2 are shown in detail in FIG. As shown in FIG. 5, the DTC 3 consists of two fetch-only data transfer circuits (hereinafter referred to as FDTC) 27 and 28 and a store-only data transfer circuit (hereinafter referred to as 5DTC) 29. B” The fetch bus 15 between the DTC 27 and the SC 4 is
Request bus 15-1 from FDTC27 to SC4.
Fetch request ("l' jJD 1+'r information bus 15-2, fetch address bus 15-3, advance bus 15-4 from SC4 to FDTC 27, fetch request additional information bus 15-5, fetch data 15-
Consists of 6. The VR write bus 18 from the FDTC 27 to the VRU 2 includes an advance bus 18-1, a write enable bus 1B-2, and a data bus 18-3. FDT
The same applies to C2a, the fetch bus 16, and the VR bowl bus 19. The store bus 17 between the li'c 29 and the SC 4 consists of a request path 17-1, a store request additional information bus 17-2, a store address bus 17-3, and a store data bus 17-4.
The VR entertainment bus between TC29 and VR[J2 consists of valid path 20-1 and store data bus 2O-21j.

FIG. 7 is a 2-square diagram of the internal structure of the FDTC 27, and hereinafter, the operation of the Fl) TC 27 will be explained using this diagram.

The output of the blur request generation circuit 27-1 is sent to the request and additional information generation circuit 27-4, and at the same time,
It is input to the mask readout circuit 27-2 and the request address calculation circuit #627-3.

The request and additional information generation circuit 27-4 generates the fetch request additional information shown in FIG. is F, F, 27-
5 and is sent to the request path 15-1. This 7
Etsute request additional information is H1M, Vo, V
+, Co, C+, and I. 1-i-0,1, 8 bytes and 4 bytes respectively)? Order, M-Or 1
When , single request, compound request, vo
For Vl, the first 4 bytes of 8 bytes are valid, for Vl, the latter 4 bytes of 8 bytes are valid, and for C0, ■. The mask value corresponding to C
8 is the mask value corresponding to vl, ■ is VLR- when M-1
74 respectively. This fetch request additional information is sent to the fetch request additional information bus 15-2 via F, F and pillars 27-6. In synchronization with these, the request address generated by the request address calculation circuit 27-6 is sent to the address bus 15-6 via F, F, #P27-7. An example of the time chart during this period is shown in Fig. 8, and the MS at that time is 0) = h
A bank busy time chart is shown in FIG. Figure 9 shows a 4-byte vector of consecutive addresses A= (A(o+,
A(1).

The case of a vector load instruction that loads . . . Aln) ) is shown.

VR4 included side 1 circuit 27-14 sends the fetch request additional information to bus 15-5, F, F, group 27-12.
If the request is a combination of two 4-byte fetches, the advance bus number is generated twice and sent to the bus 18-1.

At this time, mask values giving aliases to these two advances are sent to bus 18-2. Data bus 1b-6, F, F,
The 8 bytes of fetch data sent via the group 27-13 are controlled by the select circuit 27-16.
Data bus -18-
Sent on 5th.

Corresponding to the case of FIG. 8, the time chart during this period is shown in FIG. As can be seen from Figure 10, Advance 2 for a request that combines the 0th element and the 1st element
When it receives 7-11, it knows this from the H pit and M bit in the fetch request additional information 27-12,
Send 2 advance 18-1s to VRU. The write enable 18-2 at this time is generated from bits C8+C4 of the fetch request additional information 27-12.

In this example, in the case of VLR-4, 4-byte data is sequential in the forward address direction, so
co becomes the write enable for the 0th element, and CI becomes the write enable for the 1st element.
It becomes a write enable for the support.

In the case of V=R--4, that is, when the 4-byte data is consecutive in the opposite address direction on the distortion, the I bit in the fetch request additional information 27-12 becomes 111, and the 01 bit becomes the o-th bit. Enables the element to be written,
The co bit becomes the write enable for the first element. The same can be said of the select circuit 27-16.

In the case of consecutive 4-byte address order as in this example, the upper 4 bytes of the 8-byte fetch data 27-13 transferred from the address are first cut out and sent to the data bus 18-6 as the 0th element data. Sent out. Data bus 18-3
10' is entered in the lower 4 bytes. In the next cycle, the lower 4 bytes of 7-etch data 27-13 are cut out, and the first
It is sent to the upper 4 bytes of the data bus 18-6 as element data, and "01" is entered in the lower 4 bytes.VLR=-4
In this case, conversely, the lower 4 bytes of the 7 etcher 27-L5 are cut out as data for the O-th element, and in the next cycle, the upper 4 bytes are cut out as data for the 1st element. VR
In U2, the advance 18-1 updates the VR write pointer, and the write enable 18-
2 determines whether or not the VR write data 18-5 can be written.

For double-precision instructions, fetch request additional information 2
Each bit of H, M, and I in 7-12 is always 0°, so that the equations are -v, , co-c. Also, fetch data 8 bytes 27-15 are VR write data 8 as is.
Sent to VRU2 as byte 18-6.

Next, the operation of the 5DTC 29 will be explained using FIG. 11. The variable transferred from the VRU 2 via the variable path 20-1 passes through l;', 1;', 29-1,
At the same time as being sent to the request and additional information generation circuit, it is input to the mask reading circuit 29-6 and the request address calculation circuit 29-4. The request and additional information generation circuit 29-5 uses the mask value 29-12 and the 8-byte address 29-13 to generate the request and the sixth
The store request additional information shown in Figure (2) is generated.

This m information with store request consists of Vo = VI. For VO, the first 4 bytes of 8 bytes are valid, ■1 is 8
Each indicates that 4 adult cow bites are valid. V of this store request additional information. +V is sent to the request bus 17-1 and the store request additional information path 17-2 via the F, F, 29-7 and F, F, groups 29-8, respectively. In synchronization with these, the request address generated by the request address calculation circuit 29-4 is sent to the address bus 17 via F, F, group 29-9.
-3. In addition, the 4 bytes of store data set in the upper 4 bytes of F, F, group 29-2 via the store data bus 20-2 are combined into two elements and are stored in F, F, group 2.
9-10 and sent to the store data bus 17-4. A time chart during this period and a puncture busy time chart of Kouno Valley are shown in FIG. 12 and FIG. 16, respectively. Figure 16 shows the 4-byte vector C-(C(0),
A case of a vector store instruction that stores C(1)-C(n)) is shown.

〔Effect of the invention〕

According to the present invention, it is possible to process multiple elements at once in both vector fetch/store functions by using a mask, and it is also possible to request store processing of elements that should be suppressed by mask values. Since it can be suppressed from the moment it occurs, it is possible to avoid bank conflicts between elements in the same vector fetch/store instruction processing, reduce bank conflicts between mantissa vector fetch/store instructions, and improve the processing speed of those instructions. can be greatly improved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a configuration example of a vector processing device, FIG. 2 is a conceptual diagram of bank busy time in general vector fetch/store instruction processing, and FIGS.
FIG. 5 is a bank busy time chart in byte address continuous vector fetch store command processing, and FIG. 6 is a block diagram of a data transfer circuit in an embodiment of the present invention.
and (2) are diagrams for explaining fetch and store request additional information, Figure 7 is a diagram showing the internal structure of the fetch data transfer circuit, and Figures 8 and 10 are the fetch data transfer circuit. FIG. 9 is a bank busy time chart of the MS corresponding to FIGS. 8 and 10. FIG. 11 is a diagram showing the internal structure of the store data transfer circuit, and FIG. FIG. 16 is a time chart of an example of the operation of the store data transfer circuit and a bank busy time chart of the case, respectively. 1...MS, 2...VRU, 3...DTC. 4...SC, 5,6...ALU. 7-14...■ Read/write path, 15-16...
・Fetch pass, 17...Store pass, 18-19・
...VR honorable pass, 20...VR readout pass, 21
~26... Data bus for ALU, 27-28... Data transfer circuit for fetch, 29... Data forwarding circuit for store, 27-1... Pre-request generation circuit, 27-2.2
9-3...Mask readout circuit, 27-5, 29-4
...Request address calculation circuit, 27-14...
VR control circuit, 27-4, 29-5... request and additional information generation circuit, 27-16, 29-6
...Select circuit. Figure 1 Part 3! -Sakeichi 4th-Kai Tazu, 1 Takanabe Tomomi 8Figure 27I Φ 3 0 ■ DeL request l Tarl 1
2. Φ0 0. O'NoQuest 1 Day 3 7 Request I'L 2s 2. 2ρ q■ 6. ■ Ato Noku
Two people 27-no 3 @, ■ ■, ■ ■, 5 6. the law of nature
Hue, 7th District/B-30 ■ ■ ■ ■ ■ ■
■ vsl＞Mite°1 Yushu it 品蕃72 Figure/7-1 O! ■ 4 Request

Claims (1)

[Claims] (1) A main memory device, a plurality of vector registers for storing vector data, a data transfer circuit that controls data transfer between the main memory device and the vector registers, and a main memory access request from the data transfer circuit. In response to a fetch request, the fetish data read from the main memory is transferred to the data transfer circuit, and in response to a store request, the store data received from the data transfer circuit is transferred to the main memory. A vector processing device having a storage control device that transfers data to the main storage device, in which requests for a plurality of vector elements processed by the data transfer circuit are combined into one and transferred to the storage control device; The main storage device processes the request as a single request, and in response to a fetch request, the data transfer circuit divides the fetch data into data corresponding to a plurality of requests and sequentially transfers the data to the vector register,
In response to a store request, multiple store data 'l7?' are transferred from the vector register. 1. A vector processing device characterized in that the data is attached to one request in the data transfer circuit, transferred to the storage control device, and stored in the main storage device all at once.