JPS5854477A - Controlling method of main storage - Google Patents

Abstract

PURPOSE:To increase substantially the occupied time of a main memory, by making the preceding request substitute for the amount of the next request if the accompanied address is consecutive between the two continuing requests. CONSTITUTION:The occupied time of the main memory of a CPU, etc. (shorter than the main memory occupied time of a vector unit VP) is substantially increased to avoid an overflow. In this case, a CPU13, etc. executes a store request to a main memory 11, and this continuity is monitored to detect that an address ADK acompanied to the K-th store request and the corresponding address ADK+1 of the (K+1)-th order are continuous. Thus the (K+1)-th request is cancelled to be substituted with the K-th request. At the same time, the coincidence is secured between the addresses ADK and ADK+1. As a result, the occupied time of the main memory is substantially increased for the CPU13.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a main memory control force method, particularly to a main memory control force method suitable for application to an information processing system including a vector unit.

An information processing system generally includes a main memory t (MM) and a central processing unit (CPU) that utilizes the main memory t (MM).
) or Channel Pro 7, Su (CHP), these CPUs, CHP and the above M M (Maln M@m
and a storage control unit (MCU) that controls the memory.

In recent years, a vector unit (VU) has come to participate in addition to the CPU, CHP, etc. mentioned above. This V
U (Vsetor Unit) is executed by so-called pipeline processing, and can process a large amount of data at extremely high speed. For this reason, the frequency of use of the MM by the vector unit (VU) is extremely high compared to the CPU and CHP. Therefore, a priority circuit (PRIO) is provided in the MCU, and these V U
, CPU, and VU, which determines the priority regarding the MMO usage order for CHPK.
C) Since the frequency of use of MMK is much greater than that of CPU and CUP, MMO1 interleaving is increasing and increasing the data supply capacity to v'u, but the frequency of use of CPU and CHPKMM is increasing. If the main recycle was occupied, the VU waiting time would be long (and the overall calculation speed would not increase much).

Therefore, the f-tility circuit PRI is installed in the MCU.
In addition to O, an interface circuit INT is provided, and the CPU
, CHP is connected to Mukuro PRIO via INT, while vector unit VU is accessed from PRIO at any time.
With the adoption of a system that allows direct access to IO, these 18 guns were equipped with /gutsu fame cages exclusively for CUP, and CHP's fjp4ite request tPRI was installed.
Efforts are being made to reduce the frequency of accesses to PRIOK by converting O into a 64-byte request in the same way as a CPU load request. However, although the CPU and CEP can perform a store request to the MM at a maximum rate of once every 3τ (τ is one machine cycle), the store request from the MM via the INTt is executed at a maximum rate of once every 5τ. I feel depressed. In this case, if CPU and cup increase the store refresh rate at a rate of 3τ/1 time, an overflow will occur if they are processed at a rate of 5τ/1 time.

Therefore, an object of the present invention is to propose a main memory control method that can eliminate the above-mentioned overflow.

In accordance with the above object, the present invention, when executing a store request from the CPU or CHP to the MM, monitors a series of store addresses attached to each of the series of store requests, (k is a natural number) and the store address ADk attached to the (k+
1) If it is detected that the store address AD(k+t) attached to the th store request is a continuous address, the (k+1) 11th store request is canceled and the previous tsk The present invention will be described below in accordance with the drawings.

In the 6 diagrams showing an example of a general information processing system 0IIA, 11 is the main memory (MM), 12 is the storage control unit 11 (MCU), and 13 is the central processing unit. (CPU), 14 is Channel Grosse, t
(cup), 15 is one, 1/t"'=y)CVU)
? be. These CPU1B, cHp14, and VUIS compete to utilize the MMII tube. Then, the priority 4 circuit (PRIO) 16 in the MCU 12 performs traffic min+ in response to the conflict of MM usage. An example of traffic control in this case is v tr -t V U -2 V U -3 / This is an arm turn. According to this, PRIO16
d. If there is a store/restore suite from the CPU 13 or CMP 14, the client must give up exclusive possession of the MMII one in four times, and the V
The throughput of data supply to U does not increase.

Therefore, the idea was to introduce an interface circuit. This interface circuit reduces the number of accesses by providing a buffer memory for the CHP described above. Figure 1B is a block diagram showing a second example of a general information processing system. As shown in the figure, the aforementioned interface circuit (INT) 17 is further provided within the storage control unit (MCU) 12. In this way, the throughput of the vector unit VU 15 is improved.

However, due to the presence of lNT17, CPU13, C
The processing speed regarding HP 14 will be reduced.

The tuna 2 diagram is stored in the information processing system of 1B.
FIG. 2 is a time chart for explaining that the processing speed of requests decreases. FIG. Column (A) in this figure is, for example, the CPU
13, it is shown that it is possible to execute the Kodoor Rifnist at a rate of 3τ/1 time, and the operation in the system of FIG. 1A, for example, resonates with this. First, when a store request is sent from the CPU at timing (2), one time elapses in so-called inter-device transfer until it reaches MCUK, and its acceptance is issued by the notification ACPT vtMCU, and 2τ elapses before it reaches CPUK. According to the system of FIG. 1B, the interface circuit INT and! Lyorip 4 circuit P
Since it passes through RIO, the actual execution time is 5τ/1
The ratio will be times. This figure is shown in (
This is column B). Note that MMGO represents main memory activation, and nine of the machine cycles τ with black circles are dummy cycles that can be inserted to simplify the logic. This MMCOR12τ is applied and the signal is transferred to the lNT17.

Therefore, in the present invention, the accesses that occur at a maximum rate of 3τ71 times are reduced to a rate of 5τ71 times, and the shortfall in accesses caused by this is covered by a special access method. According to this special access method, the access rate of 5τ/1 time is 6
The rate will be increased to f/2 times. This is a store
This method focuses on the continuity of addresses and responses, and if it is found that the store addresses are consecutive, the store address AD(k+1) attached to the next store request will be set in advance to the store address AD(k+1) of the previous store request. Since it is determined at runtime, there is no information regarding the previous store request.
There is no need to repeat exactly the same operation for the current store request, and the processing flow can be partially omitted. The time available due to this omission can be used to cover the overflow described above.

Whether the store addresses are consecutive or not is determined by the address M-
and D(k+1)O can be easily discovered under two conditions: both least significant bits do not match and all bits other than the least significant bit match. This coincidence switches the coincidence flag, which will be described later, from 10# to "1". To briefly explain the discovery of continuity, addresses 116 and lII are continuous, or lOl and 106 are also continuous.

Note that the bit marked with * is the least significant bit. Also, when there is such continuity, the previous address AD
Relocating the current address An(k+1) from k is extremely easy with a simple bit inversion operation.

FIG. 3 is a time chart for illustratively explaining how the method according to the present invention can increase the number of shots per liter to 6τ/2 times.

Column (4) of this time chart is the same as column (6) of Fig. 2 above, but when referring to column 俤), it can be seen that two MMGOs exceeded IN'r17 at 6τ(■-■). I know that there is. This is the match flag (dotted line F in the figure) 0.
Detection (detection of logic @1#) Under O, as shown in the diagram ■±1
Just by manipulating the address, it is possible to execute the request following the riff'est in (■). The operation of ■±111 here corresponds to the above-mentioned "simple bit inversion operation" of the least significant bit F.

FIG. 4 is a diagram showing a ninth example of hardware for detecting continuity of store addresses.

In this figure, time D is a store address attached to each store request, and theoretically it can be issued at a maximum rate of 3τ71 times. Therefore, focusing on the continuity of the addresses mentioned above, originally the PRIO circuit 14 or 5τ/
The number of times to be processed at a rate of 1 times is increased to 6τ/2 times (note that the continuity of addresses is remarkable, for example, in so-called Moots instructions). For this reason, please enter Zosta 41 once.
Hessed address AD￥t, address queue 42
Then, go to Pa, Fa, and store. The address queue consists of registers 42-1, 42-2, . . . , 42-n belonging to 42 companies. Here, the comparison circuit 43 determines the continuity between the address ADk associated with the 1st store request and the address AD(k+1) associated with the (k+t)th store request. This comparator circuit 43 stores store addresses Bi, ) (00 to 28) and Bi, ) (00 to 2).
Perform tests 7) and (28). In other words, the address ADk (register 42-1
(stored in register 41) and address AD(k+1) (stored in register 41) related to the current store request, that is, (OO~27)k and (00~27)(k+1) Check the coincidence/mismatch of (28)k and (28)k+t. Bit (00~
If there is a match for (27) and a mismatch for (28), a match flag Fi"l" is set to indicate that there is address continuity.The comparison circuit 43 compares bits (00
-27) and (28) and add 41 gog(v) works. Also, each register 42-1.42-2
...42-n has valid flags V (Vl, V2
...Vn) is also attached.

FIG. 5 is a block diagram showing an example of the configuration of an f2 priority circuit when implementing the method of the present invention.

In this figure, 51 is a continuous processing circuit, which cooperates with the continuous detection circuit in the interface circuit INT illustrated in FIG. 52 is a logic circuit, and 53 is a request reception register group. These register groups 53 are CPU, C
It is not HP, but the vector uni, ) VU or store request group. The logic circuit 62 accepts access requests regarding the CPU and CHP from the circuit 51 system and access requests regarding the vU from the register group 53, and performs priority checking and busy checking (whether MM activation is possible or not). MMG
O (main storage outer case boot code) and accompanying address A
Send D.

By the way, the continuous processing circuit 51 receives the match 7F and the address ADt shown in FIG. 4, and inputs them to the select gates 51-1 and 51-2, respectively. This selection f-)it is normally set to address D@fully open. In other words, registers F, R, and V contain the fourth
The contents of the match flag, address (00-28) and valid flag V shown in the figure are entered. This flag indicates whether the store request related to the address is valid/invalid, and is normally valid ("1").

Here, assume that a match flag FK logic 11# is input. Then, at this time, register FK""1# is input, and select signal S (@1") is set to select r-) 51-1.
5l-2t-Switch to the opposite mode to the above mode. Then, the seventh controller 51-2 simply inverts only the least significant bit (bit 28) of the previous address (by the inverter 55) and returns it to the register R.

This means that the address associated with the (k+1) store requests is the same as the address ADk and shim D(k+1). At this time, the match flag is forcibly reset to zero by the inverter 54 and returned to the register F from the gate 51-1. Since the store request (k+1) this time has to be canceled, Paris and flag V are also forcibly converted to @Om by the NAND gate 56. Therefore, jIk stores/
This means that the request processes store accesses for two consecutive addresses (see Figure 3).
See B).

Note that the store data corresponding to the (k+1)th store request is sent after the store data corresponding to the first store request is sent. In other words, the timing for sending the store data pipe corresponding to the lk-th store request accompanied by the match flag Ft is determined by lk.
Assuming that it is Nth time from the MMGO for the th request, the (k+l)th store data is 1ii(
It is sent from the (k+1)th MMGO to the Nth clock.

As explained above, according to the present invention, it is possible to increase access processing from the conventional 5ii once to 6ii twice, and the effect is great when applied to a system where a vector unit and a normal CPU@ cooperate. It is.

[Brief explanation of the drawing]

FIG. 1A is a block diagram showing a first example of a general information processing system, and FIG. 111 is a block diagram showing a second example of a general information processing system.
FIG. 2 is a time chart to demonstrate that the processing speed of store requests is reduced in the information processing system of FIG. 1B; and FIG. , 5ii one access to 6ii
Figure 4 is a block diagram showing an example of hardware for detecting continuity of store addresses; Figure 5 is a diagram for implementing the method of the present invention. 11... Main storage device, 12... Storage control device, 13
... central processing unit, 14 ... channel processor,
15... Vector unit, 16... Priority circuit, 17... Interface circuit, 42... Address/I? Uni 43...comparison circuit. Patent Applicant Fujitsu Limited Patent Application Agent Akira Aoki Patent Attorney Kazuyuki Nishidate Patent Attorney Yukio Uchida Akira Yamaguchi -14-1-@14-? Kari II-τ sword
- in - + l' 1 Procedural amendment dated August 11, 1980, Director General of the Patent Office Kazuo Sugi1, Indication of the case 1982 Patent Application No. 1528962, Name of the invention Main memory control power method 3, Relationship with the case of the person making the amendment Name of patent applicant (522) Rinjutsu Co., Ltd. 4, Agent 5, Subject of amendment (1) Detailed explanation of the invention in the specification (1) Column (2) Drawings (No. Figure 2 @) 6,? 1 Correct contents (1) The detailed description of the invention in the specification will be amended to the following. "It will happen," he corrects. (a) 9th member tθ line r PRIO circuit 14J is corrected as r PRIO circuit 16J. (2) Change “τ” on the right hand side in ■ in Figure 2 of the original drawing to “
◇ 7. List of documents with #S

Claims (1)

[Scope of Claims] 1. An information processing system comprising at least a main storage device and a central processing unit that generates a store request to the main storage device via a storage control device, comprising: When a device etc. executes the store request to the main storage device, a series of the store requests are executed.
The continuity of a series of store addresses attached to each request is monitored, and the store address Dk attached to the l h (h is a natural number) store request and the (k+1)th store request are When it is detected that the associated store address An(k+1) is continuous, 1fE(k+1)th store request is canceled and the previous @ is made to handle the @th store request, and the above Store address AD
kt- A main storage control method characterized in that address processing is performed so as to match the address system D(k+1).