JPS6227837A - Main memory access system - Google Patents

Abstract

PURPOSE:To evade deadlock of a main memory access system by invalidating an exclusive control request held by a transmitting means and delivering an exclusive control end request to a main memory in case an exclusive control request is produced from another main memory requester while the first exclusive control request is accepted. CONSTITUTION:An exclusive control request is delivered from an operand request part 2 of an execution processor 1 for each same clock while the exclusive control request delivered from an instruction request part 4 of the processor 1 is accepted by a system controller 23 and the exclusive control request is processed. The information on the above-mentioned operations is given to a lock-up detecting part 17 from an exclusive control request part 5 in an instruction request part 4 through a signal line 14. The part 17 invalidates the exclusive control request of a register 9 via a signal line 18 and also gives a re-extracting request of an operand to the part 2 via a signal line 19 after the part 17 detects that the exclusive control request is stored in the register 9 and also that said exclusive control request fails. In such a way, a deadlock can be evaded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a main memory access method, and in particular, to a dead access method in a processing device configured to send a plurality of exclusive control requests to a main memory device through a single transmission means. Concerning lock avoidance techniques.

Exclusive control is performed to avoid multiple accesses to the common data area of the main storage device.

This exclusive control is necessary between each processing unit in a multiprocessor system where the main memory is shared by multiple processing units, and also requires multiple If there is a main storage request source, this is also required among these multiple request sources.In general, the exclusive control request is issued for a specific division unit (referred to as a lock unit) of the main storage device, and When an exclusive control request is accepted, a lock is placed on the lock unit.Here, the lock is for the exclusive control request, and normal memory access is not inhibited.

[Conventional technology]

FIG. 2 is a block diagram of a system implementing a conventional main memory access method, in which two execution processing units 32 and 33 and two input/output processing units are connected to the main memory bag w30 via a system control device 31. 34. Connect 35 and execute processing device 3.
2.33 shows a multiprocessor system in which the main storage device 30 is shared.

The execution processing unit 32C; is an operand requesting unit 36. There are two main memory request sources of the instruction request unit 37, and an operand request issued from the operand request unit 36 (operand write request, operand read request, exclusive control request accompanying them, exclusive control paired with this exclusive control request) The command requests issued from the command request unit 37 (there are various types such as an instruction fetch request, an accompanying exclusive control request, and an exclusive control termination request paired with this exclusive control request) are as follows: It is selected by the selector 38 according to a predetermined priority order and loaded into the register 39. This priority is normally highest for operand fetching, next highest for instruction fetching, and lowest for operand writing.Selector 40 selects the output of register 41 when there is a valid request in register 41; If there is no valid request, register 39 is selected and its contents are loaded into register 41. This load is performed when the contents of the register 41 are other than exclusive control requests.
1 is received by the system controller 31. However, when the content of the register 41 is an exclusive control request, the selector 40 selects the selection from the register 41 even after the exclusive control request is received by the system control device 31.
The register 39 is fixed at
The contents of are loaded into register 41. Note that the same configuration as above is also provided on the execution processing device 33 side.

For an exclusive control request sent to the system control device 31, the success or failure of locking is determined by the execution processing bag that issued the exclusive control request! Reported on 32°33. If the lock is successful, the selector 40 in the execution processing unit is switched to accept a new request from the register 39, and if the lock has failed, the exclusive control request is again sent from the register 41 to the system control device. 31.

Now, considering the case where exclusive control requests are issued from the execution processing units 32 and 33 for a certain lock unit of the main storage device 30, the two exclusive control requests are
1, the system controller 31 reports lock success only to the only executing processor. Then, in the execution processing device on the side where the lock was successfully executed, the next request is loaded from the register 39 to the register 41 via the selector 40, as described above. On the other hand, the execution processing device on the side where the locking has failed holds the exclusive control request in the register 41 as described above, and continues to send the exclusive control request to the system control device 31 until the locking is successful. For this reason,
Subsequent instructions will have to wait until the lock is successful.

The execution processing device that successfully acquired the lock performs processing that requires exclusive control, and when that processing is completed, the exclusive control termination request is sent to the system system via the same path as the exclusive control request. 11 device 31. In response to this, the system control device 31
becomes ready to accept new exclusive control requests for that lock unit. Therefore, if another execution processing unit issues an exclusive control request for the same lock unit, the system control unit 31 reports lock success to that execution processing unit, and the other execution processing unit also requires exclusive control. processing becomes possible.

[Problem that the invention seeks to solve]

By the way, in the configuration shown in FIG. 2, when exclusive control requests due to instruction fetching and operand fetching are simultaneously issued from the same execution processing unit to the same lock unit, the selector 38 first selects whichever has the higher priority. The other exclusive control request is selected, and the register 39. Selector 40. The exclusive control request is sent to the system control device 31 via the register 41, and at the time when the success of the lock is reported, the subsequent exclusive control request is sent to the register 39. Selector 40. register 41
It is sent to the system control device 31 via. However, since the previous exclusive control request has already been successfully locked, the subsequent exclusive control request is not accepted by the system control device 31 and remains held in the register 41.

Therefore, even if an exclusive control termination request is issued from the main memory request source that issued the previous exclusive control request, this exclusive control termination request cannot be loaded into the register 41, and the system control device 31 is prompted to terminate the exclusive control. If the request cannot be sent and the exclusive control end request cannot be sent, the exclusive control request held in the register 41 will not be accepted, so a so-called deadlock occurs at this time.

One way to avoid such a deadlock is to provide a means in the execution processing unit to detect whether or not the main memory request source at the current location is performing exclusive control processing. The purpose is to prevent the main memory request source from issuing a new exclusive control request.

However, with such a configuration, even if the lock units subject to exclusive control requests are different from each other, subsequent exclusive control requests are suppressed, resulting in a problem that performance deteriorates significantly.

An object of the present invention is to avoid deadlocks as described above without degrading performance.

[Means for solving problems]

In order to solve the above problems, the present invention has a plurality of main storage request sources, sends exclusive control requests issued from each request source to the main storage device through a common transmission means, and The main memory access method in the processing device is configured such that when a control request is not accepted, the exclusive control request that is not accepted is held in the transmission means and repeatedly sent to the main memory until the control request is accepted. When an exclusive control termination request is issued from another main memory request source while the exclusive control request held in the transmission means is not accepted, the exclusive control request that monopolizes the transmission means is invalidated and the exclusive control termination request is In addition, the main memory request source that issued the invalidated exclusive control request is instructed to reissue the exclusive control request.

[Effect]

If an exclusive control request issued by one main memory request source is accepted and exclusive control processing is being performed, if another main memory request source issues an exclusive control request for the same lock unit, the previous exclusive control request is Since the control request has already been accepted, subsequent exclusive control requests will not be accepted, resulting in a situation in which the transmission means is monopolized. However, if such a situation occurs, the exclusive control request held in the transmission means will be invalidated, so the exclusive control end request from the main memory requester that issued the previous exclusive control request will not be sent to the transmission means. It becomes possible to send the data to the main storage device via the computer. In addition, since the main memory request source whose exclusive control request has been invalidated is instructed to reissue the exclusive control request, by sending the exclusive control request again based on the reissue instruction, the exclusive control termination request Coupled with this, the exclusive control request is also accepted by the main memory request source, and deadlock is avoided.

〔Example〕

FIG. 1 is a block diagram of a data processing system according to an embodiment of the present invention, in which 1 and 20 are execution processing units, 21 and 22 are input/output processing units, 23 is a system control unit, and 24 is a main storage unit.

The execution processing device 1 includes an operand requesting section 2, an instruction requesting section 4. A main memory request mechanism including a selector 6.8, a register 7.9.10, a lockup detection section 17, etc. is provided. During the main memory request mechanism, register 9 and signal line 16
Transmission means including, etc. are included. A main memory request mechanism having a similar configuration is also provided in the execution processing unit 20.

Requests to the main storage device 24 are issued from the operand request section 2 and the instruction request section 4. Operand request unit 2 and instruction request unit 4 each independently generate main memory requests, and both requests are selected by selector 6 and loaded into register 7. When there is only one request, the selector 6 selects the requested main memory request, but when two main memory requests occur simultaneously, it selects one of the requests based on a predetermined priority order. Also, selector 6 is register 7
Selector 8 will not accept a new request while a valid request remains in register 9. Selector 8 will accept a request from register 7 if there is no valid request in register 9, and selector 8 will accept a request from register 7 if there is a valid request in register 9. Select the output of

The main memory request loaded into register 9 is transmitted to system controller 23 via signal line 16.

Is the system control device 23 each execution processing bag? I! 1. Accepts requests from 20 and interfaces with the main storage device 24.

In addition to normal main memory requests, the operand request unit 2 and instruction request unit 4 also request exclusive control of the main memory.

A request to terminate exclusive control can be issued. The exclusive control request issued from the operand request unit 2 or the instruction request unit 4 is
Register 9 via selector 6, register 7, selector 8
In a normal main memory request, when the request is received by the system controller 23, the selector 8 selects the register 7 to accept the next request.
In the case of a 1114 request, the request is sent to the system controller 23.
The exclusive 111J request remains in register 9 until it is confirmed that it has been accepted.

Whether or not the exclusive control request is accepted is loaded from the system control device 23 into the register 10 via the signal line 11. If the exclusive control request 1g has been accepted, selector 8 selects register 7 to enable acceptance of the next request; if no exclusive control request has been accepted, selector 8 selects register 9 again.
An exclusive control request is sent from the system controller 23 to the system controller 23. Thereafter, similar operations are repeated until the exclusive control request is accepted by the system control device 23.

The operand requesting unit 2 or the instruction requesting unit 4 issues an exclusive control request and, when the request is accepted, enters exclusive control processing. This exclusive control process is a process that requires strict exclusive control over the system's shared memory, such as redistribution of machine hardware resources.

The operand requesting unit 2 or instruction requesting unit 4 that has completed the exclusive control processing transfers the main storage device I! In order to transfer the exclusive control right of the shared area of 24 to another processing device, an exclusive control termination request is issued. This exclusive control termination request is transmitted to the system control device 23 through the same route as the exclusive control request.

Now, the exclusive control request issued from the operand request unit 2 of the execution processing device 1 is accepted by the system control device 23,
Let us assume that while exclusive control processing is being performed, an exclusive control request is issued from the command requesting unit 4 of the same execution processing device 1 for the same lock unit as the exclusive control request. In this case, the lock unit for which the instruction requesting unit 4 made an exclusive control request has already been locked by the operand requesting unit 2 of the same execution processing unit 1, so the exclusive control request issued by the instruction requesting unit 4 is It is not accepted by the device 23.

On the other hand, the operand requesting unit 2 eventually ends the exclusive control process and returns to the exclusive side? 11 Issue a termination request 0 Even if a normal main memory request is issued from the operand request unit 2, the register 9
Since the exclusive control request located in the register 7 occupies the signal line 16 leading to the system control device 23, the normal main memory request issued from the operand request section 2 is made to wait in the register 7. However, in the case of an exclusive control termination request, the exclusive control request section 3 provided in the operand request section 2 reports to the lockup detection section 17 through the signal line 13 that the exclusive control termination request has been issued. Then, the lockup detection section 1
7, the sending of the exclusive control termination request is reported, and register 9
If it is determined from the contents of the register 10 that the exclusive control request remains and that the failure of the exclusive control request has been reported from the system control device 23, the exclusive control request of the register 9 is invalidated by the signal line 18. At the same time, a request for re-fetching the instruction is notified to the instruction requesting section 4 via the signal line 15. As a result, the exclusive control end request remaining in the register 7 is selected by the selector 8, loaded into the register 9, and sent to the system control device 23.

Further, the instruction requesting unit 4 that has received the instruction re-fetching request,
In response, an exclusive control request is issued again. At this time, since the exclusive control end request from the operand request unit 2 has already been sent to the system control device 23, the exclusive control request issued from the command request unit 4 is accepted. become.

Further, an exclusive control request issued from the command requesting section 4 of the execution processing device 1 is received by the system control device 23, and while the exclusive control request is being made, the operand requesting section 2 of the same execution processing device 1 sends the When an exclusive control request is issued for the same lock unit as the exclusive control request, the exclusive control request from the operand request unit 2 temporarily occupies the register 9. However, in this case as well, when an exclusive control termination request is issued from the command requesting section 4, the exclusive control requesting section 5 in the command requesting section 4 notifies the lock amplifier detection section 17 through the signal line 14, and the lock-up detection section When detecting that the exclusive control request remains in the register 9 and that the exclusive control request has failed, the controller 17 invalidates the exclusive control request in the register 9 via the signal line 18 as described above, and also outputs the signal. Since an operand re-fetching request is issued to the operand request unit 2 via the line 19, deadlock is avoided.

Note that in the above embodiment, when the exclusive control request from the instruction requesting section 4 remains in the register 9 and it becomes difficult to send the exclusive control termination request from the operand requesting section 2, and when the exclusive control request from the operand requesting section 2 Although we have assumed both cases in which the exclusive control end request from the instruction request unit 4 is difficult to send due to the request remaining in the register 9, depending on the computer architecture, either the former or the latter may not occur. Conceivable. In such a system, for example in a system where the latter cannot occur, the controller 5 of FIG. The signal lines 14 and 15 may be omitted to avoid deadlock only in the former case.

〔Effect of the invention〕

As explained above, according to the present invention, while an exclusive control request issued by a main memory request source in one processing device is being accepted, another main memory request source in the same processing device When an exclusive control request is generated from a single transmission means and it becomes difficult to send an exclusive control termination request because only one transmission means is occupied, the exclusive control request held in that transmission means is invalidated and the exclusive control termination request is not sent. Since it is possible to send the data to the main storage device side, deadlock can be avoided. In addition, the main memory request source that issued the invalidated exclusive control request is instructed to reissue the exclusive control request, so the main memory request source that received the instruction can send the exclusive control request again. The exclusive control request can be accepted.

Furthermore, a method is provided in which a means for detecting whether exclusive control processing is currently in progress is provided in the processing device, and if exclusive control processing is in progress, no new exclusive control requests are issued from each main memory request source. According to the above method, even if the lock units subject to exclusive control requests are different from each other, subsequent exclusive control requests are suppressed until the previous exclusive control processing is completed. According to the above, since generation of exclusive control requests from each main memory request source is not suppressed, exclusive control requests in different lock units can be immediately accepted, and performance can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a data processing system implementing the main memory access method of the present invention, and FIG. 2 is a block diagram showing an example of a data processing system implementing the conventional main memory access method. In the figure, 1 and 20 are execution processing units, 2 is an operand request unit, 4 is an instruction request unit, 21 and 22 are input/output processing units, 23 is a system control unit, and 24 is a main storage device. Patent Applicant: NEC Co., Ltd.＞Sumi,',;, , , 1
-11...A Representative Patent Attorney Susumu Uchihara Figure 1: Block diagram of an embodiment of the present invention

Claims (1)

[Scope of Claims] A system having a plurality of main storage request sources, and transmitting exclusive control requests issued from each request source to the main storage device through a common transmission means,
When the transmitted exclusive control request is not accepted, the main unit in the processing device is configured to cause the transmission means to retain the exclusive control request and repeatedly transmit it to the main storage device until the exclusive control request is accepted. In the storage access method, when an exclusive control termination request is issued from another main memory request source while the exclusive control request held in the transmission means is not accepted, the exclusive control request for exclusive use of the transmission means is invalidated. A main memory access method characterized in that the exclusive control termination request can be sent, and the main memory request source that issued the invalidated exclusive control request is instructed to reissue the exclusive control request. .