JPH01305457A - Main storage access request control system - Google Patents

Abstract

PURPOSE:To efficiently process access requests from plural request origin devices by resetting the access request from another request origin device for an address on which a certain request origin device desires to execute to make access exclusively. CONSTITUTION:When request information is set on a request register 1, the request information and a register number are set on a request port 5 at a request selection part 25 according to a priority order. The address to which a certain request origin desires to execute to make access exclusively and the register number are set on a lock register 15, and they can be cancelled by a cancel request from the same request origin device. A comparator 14 compares the lock register 15 with the content of the request port 5, and outputs a signal when the register numbers are different and their addresses are the same. A precedence control part 22 resets the request port according to the signal. At this time, a lock control part 21 blocks the set of the request register 1, and holds the request information.

Description

[Detailed Description of the Invention] [1 Required] Regarding a main memory control device that has a lock function for exclusive access to main memory, even if the lock is set, access from multiple request source devices is prevented. Aiming at a main memory access request control method that can process requests efficiently, it receives request information issued from multiple request source devices and sets the request information selected in a predetermined priority order to an empty request port. Then, access to the main storage device is executed according to the contents set in the request port, and when an address match is detected between the access destination address under a predetermined condition and the lock address set in the lock register, the access is executed. If the address match is detected in the main memory control device that suppresses this, the request port is set to an empty state, and after the lock address is invalidated, the request information is reset to the empty request port. Configure it to do so.

[Industrial application field]

The present invention relates to a main memory access request control method in a main memory control device having a lock function for exclusively accessing the main memory.

[Conventional technology]

FIG. 2 is a block diagram showing an example of the configuration of a main memory control device of a computer.

The main memory control device receives main memory access requests from the central processing unit and the channel control device into a request register 1 provided corresponding to each of these devices.

The register 1 has a valid display bit 2 that is turned on when the request information is set, and the request selector 3 simultaneously selects one of the request registers l whose valid display bit 2 is set to a certain value. When selected in priority order, the selector 4 is controlled to transfer the request information in the request register 1 and the register number to one of the empty request ports 5.

The empty state of the request port 5 is determined by a valid indicator bit 6 that is set to on and becomes in use when the request information is transferred.
This is determined by referring to the signal on the signal line 126 for the glue set, which will be described later.

Simultaneously with the above transfer, a reset signal for the selected request register l is sent to the signal line 7 to turn off the valid display pin I-2 of the request register 1, thereby invalidating the contents of the request register l. Make it ready to receive the next request information from the same device.

The request information set in the request register 1 and transferred to the request port 5 includes, for example, an operation code for the main 4r2 access, an address of the access destination BQ memory area, and ♂ write data in the case of a write operation.

Note that, for example, vector processing devices that require particularly high-speed access, a request port 8 similar to the request port 5 is used.
A required number of request ports 8 are allocated to each flat file processing device, etc., and request information for main memory access is directly set in the request port from those devices.

The priority control unit 9 checks the busy state of the access destination according to the request information set in the request ports 5 and 8, and selects requests that can be accessed on a first-come, first-served basis (in the case of the same order, a fixed priority order). ) is selected and sent to the pipeline control unit 11 via the selector 10, and the request port 5 or 8 is set to an empty state by sending a reset signal to the signal line 12 or 13,
The access destination of the request is kept busy for a predetermined period of time.

The request sent to the pipeline control unit 11 is controlled by known pipeline control, and a plurality of main memory access processes are executed in parallel.

Prior to the above control by the priority control unit 9, the access destination address of the request information set in the request port 5 is compared with the address held in the lock register 15 by the comparator 14, and each comparison result indicates the corresponding lock. Display 1
6 and the lock display 16 indicates an address matching state, the priority control unit 9 suspends the processing of the corresponding request port 5, and this state indicates that the lock register 15
will continue until it is reset.

Here, the lock register 15 is a register for holding the address specified in the lock setting request from the device connected to the request register 1 and its request register number until there is a lock release request from the same device. However, a detailed explanation of lock setting and release control will be omitted.

Note that vector processing devices, etc. generally do not use areas that require exclusive access, and therefore do not need to set locks or request access to such areas. The comparator 14 is not provided for the request port 8.

The address set in the lock register 15 in this way is set for the purpose of the lock request source device exclusively accessing the address. Therefore, the comparator 14 compares the addresses and also 5 and the register number set in the lock register 15, and output a signal indicating address matching only when the register numbers are different (that is, when the lock request source and the access request source are different). There is.

[Problem to be solved by the invention]

The time for which an address continues to be occupied by the above-mentioned lock is often relatively long, for example in the case of a control information area provided in main memory for controlling a channel. but,.

According to the above configuration, when there is an access request to a locked address, the request port 5 is occupied until the lock is released and cannot be used to process other requests, resulting in an increase in access waiting time. .

This problem can be solved by providing at least the same number of request ports 5 as requesting devices and directly setting the request information, as in the case of request ports 8, but in that case, the priority control unit 9 and the comparison There is a problem in that wear under the bar such as the container 14 increases.

An object of the present invention is to provide a main memory access request control method that can efficiently process access requests from a plurality of request source devices even when a lock is set.

[Means to solve the problem]

FIG. 1 is a block diagram showing the configuration of the present invention.

The figure shows the configuration of the main memory control device, where 20 is a request selection unit that transfers the request information set in the request register 1 to the request port 5, and 21 is a comparison between the request register 1 set, etc. selected by the request selection unit 20. The lock controller 22 controls the output of the controller 14 by processing the requests set to the request ports 5 and 8 and sends them to the pipeline controller 11.
It is also a priority control unit that resets the request ports 5 and 8, and the comparator 14 compares the lock register 15 and the request port 5 and outputs an address match signal under predetermined conditions.

[For production]

Request information issued from a plurality of request source devices is received in the request register l, and the request selector 20 sets the request information of the request register l selected in a predetermined priority order to the empty request port 5, and then requests Access to the main storage device is executed according to the contents set in port 5.

At this point, an address failure is detected for the access destination address of the request port 5 and the address set in the lock register 15, and the request port 5 whose request source device is different is reset to an empty state without processing the request. .

Further, the lock control unit 21 normally issues a set signal to the request register 1 selected by the request selection unit 20, but it also monitors the output of the comparator 14, and as described above, the lock control unit 21 issues a signal set to the request register 1 selected by the request selection unit 20. When the request register 1 is reset, the reset signal to the request register 1 is suppressed so that the request information set in the request port 5 is held in the request register 1. Further, a signal for inhibiting the selection of the request register 1 is generated and sent to the request selection section 20 until the lock register 15 is reset.

With the above control method, the request port 5 is not occupied while waiting for unlocking, and access requests when there is a lock can be efficiently processed.

〔Example〕

In FIG. 1, parts with the same reference numerals as in FIG. 2 have the same functions as in the conventional case, and handle main memory access requests from the central processing unit and channel control unit to each of these devices. The data is received in the request register l provided by the server.

When the request selection unit 20 selects one of the request registers l whose valid display pin l-2 is turned on in a certain priority order, it controls the selector 4 and selects the request information of the request register 1 and the register. The number is transferred to one of the vacant request ports 5.

However, the request register 1 whose lock wait state is displayed on the signal line 23 by the lock control unit 21 is excluded from the selection target (r5) as described later.

The request selection unit 20 notifies the lock control unit 21 of the selected request register 1 and request port 5 through signal lines 24 and 25, so that the lock control unit 21 receives the notification when the lock register 15 is invalid. A signal to reset the request register 1 is immediately sent to the signal line 7.

However, when the lock register 15 is enabled, it monitors the output of the comparator 14 corresponding to the notified request port 5, and only when there is no output indicating address matching at a predetermined timing, sends out a reset signal. Monitoring comparator 1
If there is an address signal output from 4, the f5 cotton 7 heli seso I signal is not sent, the lock wait state is stored for the notified request register 1, and the lock wait state is transferred to the signal line 23. Request selection section 20 by the corresponding line
Display against. This state is maintained until the valid indication bit of the lock register 15 is turned off.

Therefore, as described above, the request information in the request register 1 that is placed in the lock wait state is held as is in the request register 1 without being reset, but is excluded from being reselected by the request selector 20 as described above. It's dark.

The request information transferred to the request port 5 is transferred to the priority controller 22 along with the request from the request port 8,
The requests that satisfy the same requirements as before are processed in the same way as before and sent to the pipeline control unit 11 via the selector 10 in priority order.
The requested port 5 or 8 is made vacant by sending a reset signal to the signal line 12 or 13, and the access destination is made busy for a predetermined period of time.

Prior to the above control by the priority control unit 22, the request port 5
The access destination address of the request information set in
5, and if the access destination address from a different request source matches the address held in the lock register 15, a signal indicating address failure is output from the comparator 14, and these outputs are compared with the address held in the lock register 15. Lock;i;+ is monitored by the control unit 21 as shown in FIG.

At the same time, the priority control unit 22 also monitors address matching output,
If address-defeat is displayed, a signal to reset the corresponding request port 5 is sent to the signal line 12 without performing the above processing, and the request port 5 is set to the vacant 4J? Reset to G.

Therefore, when waiting for a lock, the request port 5 is no longer occupied until the lock is released as in the conventional case, and the request port 5 can be immediately allocated to another request. On the other hand, the waiting request is stored in request register 1 as described above.
When the lock is released and the valid indication bit of the lock register 15 is turned off, and the lock wait state indication sent to the signal line 23 is set, the request selection section Subject to selection.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, even when an access request that waits for unlocking occurs in a main memory control device that has a lock function for exclusively accessing the main memory in the calculation stage, This has a significant industrial effect in that access requests from a plurality of request source devices can be efficiently processed without interfering with the processing of other requests.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the present invention, and FIG. 2 is a block diagram showing an example of a conventional configuration. In the figure, 1 is a request register, 3.20 is a request selection section, 4.1
0 is a selector, 5.8 is a request port, 9.22 is a priority control unit, 11 is a pipeline control unit, 14 is a comparator, 15 is a lock register, 21 is a lock control unit Block diagram showing the configuration of the present invention Conventional Block diagram showing a configuration example of

Claims (1)

[Claims] Receiving request information issued from a plurality of request source devices (
1), sets the request information selected in a predetermined priority order to an empty request port (5) (20), and executes access to the main storage device according to the contents set in the request port (11, 22). ), in a main memory control device that suppresses execution of the access when an address match is detected (14) between the access destination address under a predetermined condition and the lock address set in the lock register (15); If detected, the request port is made vacant (22), and after the lock address is invalidated, the request information is reset to the vacant request port (5) (1, 20, 21) A main memory access request control system characterized by being configured as follows.