JPS60209873A - Vector processing device - Google Patents

Abstract

PURPOSE:To reduce the frequency in main storage reference of the same data by providing a scalar register where data, which has the just preceding element number and is stored in the 0th element part of a vector register. CONSTITUTION:A series of data A2-A(N+1) taken out from a main storage 1 are written in vector registers 10 and 12 by a main storage reference control circuit 2. Contents of the vector register 10 and a scalar register 20 where data A1 is preliminarily written in the preprocessing of the processing of a vector instruction are read out, and a result VRi is written in a vector register 11, and data A(N+1) is written in the scalar register 20 by the processing to SR. The subtraction result of every element between A1-AN of the vector register 11 and A2-A(N+1) obtained in the vector register 12 is written in a vector register 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a processing device that processes vector data at high speed.

[Background of the invention]

To achieve faster processing of vector processors,
Eliminating and mitigating conflict factors in main memory operations has become a challenge. In particular, in vector processors that enable high-speed inter-register operations using vector registers, it is necessary to reduce the amount of data transferred to and from the main memory. This will be explained using figures.

In the DO loop shown in Figure 1, the result of subtraction between A(2) and A(1) is stored in 5(1), and the result of subtraction between A(3) and A(2) is stored in 5(2). So sequentially A(i+1) and A
The operation of storing the difference in (i) in S (L) is repeated for the cases where i takes a value from 1 to N. In a conventional vector processor employing a vector register as shown in FIG. 2, such processing has been performed using the following four instructions.

Instruction 1: A series of data A(2) to A(N+1) is sequentially taken out from the main memory 1 using the main memory reference control circuit 2 and written as each element data in the vector register 11.

Instruction 2: A series of data A(1) to A(N) is sequentially taken out from the main memory 1 using the main memory reference control circuit 3 and written as each element 1 to data in the vector register 12.

Instruction 3: The arithmetic unit 7 processes subtraction between data having the same element number in vector registers 11 and 12, and writes the result as element data in vector register 13 to the storage location of the corresponding element number.

Instruction 4: Read out a series of operation results written in the vector register 13 one after another, and use the main memory storage control circuit 4 to sequentially write them to addresses corresponding to S (1) to 5 (N) on the main memory 1. Write.

The connection between these vector registers, arithmetic units, and main memory control circuits has a degree of freedom, and is determined by the instruction sequence input to the processing device or by the hardware. When writing to the vector register, switch matrix 5
However, the switch matrix 6 is used when reading the vector register. The broken lines in switch matrices 5 and 6 in FIG. 2 show an example of connection when processing the program in FIG. A series of processes proceed. Since scalar register 20 and vector register IO were not used in the example of FIG. 1, the switch matrix is also shown cut-off.

The address referenced by the main memory reference circuits 2 and 3 is A(2)
~A (N) is duplicated, so A (1) ~
In order to obtain N+1 types of data of A(N+1), data references are made 2N times. Moreover, there are duplicate N-1
Regarding the reference of times, the same bank is occupied at least twice for a certain period of time called punk busy time, so
This method has the disadvantage that loss time is likely to occur due to bank conflicts. Furthermore, in addition to accesses by vector instructions, main memory is generally accessed simultaneously by scalar processing and external input/output, and in order to avoid performance deterioration due to mutual interference, unnecessary main memory is Too many references have adversely affected the performance of vector processors. In order to achieve the speed-up effect of vector registers, the conventional technology does not provide effective means for general processing between vector register data having different element numbers. 1 by shift operator
A shift command that spans the elements between the th data and the i+1th data exists in conventional machines, but because the data after the shift is lost due to logical shift, the vector length, which is the number of elements per vector data, is handled. is too complicated to use, or to make the termination process scalar processing.

There was a problem with the speed slowing down.

[Purpose of the invention]

An object of the present invention is to provide a vector processing device that can reduce the number of main memory references for the same data by half as shown in FIG. 1 without using any additional processors.

[Summary of the Invention J The device of the present invention has a plurality of vector registers and one or more scalar registers, and when vector data is stored redundantly in two vector registers so that the element numbers differ by 1, A vector register whose element number is 1 later than a scalar register that holds data to be stored in the 0th element part of the vector register whose element number is 1 earlier. The invention is characterized in that it has a command means for obtaining.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to FIGS. 3 to 5. In this example, through the processing shown in FIG. 3, a vector register VRj storing A(i + 1) where i corresponds to 1 to N, and A(1) stored in advance by preprocessing of vector processing. Using the scalar register SR that stores data, vector register VRi that stores A(i) data and A(N+1
) Uses an instruction to obtain data into the SR after processing.

However, 21 is 5R122-26 is A(2)-A(N+
1) Data storage location on vector register VRj, 3
2 to 36 indicate the storage locations of A(1) to A(N) on the VRi, respectively.

A first method according to the present invention using instructions for performing the processing shown in FIG.
The program processing procedure shown in the figure will be explained below using FIG. 4. Portions that are not particularly relevant to the present invention are based on conventional vector processors, and their explanation will be kept brief. This embodiment will be explained using the following five instructions.

Instruction 1 = The main memory reference control circuit 2 transfers a series of data A(2) to A(N+1) retrieved from the main memory 1 to the second
．． In order to read in parallel and at high speed with the third instruction, in accordance with the conventional technology, through two write ports 201 to 202,
Write to vector registers 10 and 12.

Instruction 2: Vector register IO in which A(2) to A(N+1) were written with instruction 1, and data of A(1) written in advance in preprocessing of vector instruction processing.
Read scalar register 20, vector register 11
A result such as VRi shown in FIG. 3 is written into the scalar register 20, and data A(N+1) is written in the scalar register 20 in the process for SR shown in FIG. This instruction requires three fields 101 to 103 shown in FIG. 4, which specify the operation code of the instruction, vector data VRi, and vector data VRj, respectively. In this example, there is only one scalar register, so there is no need to specify it, but considering that it will be written together with vector register 11, in field 102, vector register 1 is specified.
It is assumed that it is specified together with 1.

Instruction 3: A(1) ~ of vector register 11 in instruction 2
A (N) and A (2) to A (N+1) obtained in the vector register 11 by instruction 1 are processed in the conventional manner, and subtraction is performed for each element using the arithmetic unit 7, and the result is Write to vector register 13.

Instruction 4: By conventional processing, vector register 13
The result data obtained in Figure 4 is written to addresses corresponding to 5(1) to 5(N) of main memory 1 using main memory storage control circuit 4. Using vector register IO and scalar register 20,
Instead, the main memory reference control circuit 3 used in the prior art shown in FIG. 2 is not used. This is the first method according to the prior art.
The first command is a control command according to the present invention. Second
This corresponds to the fact that the number of references to main memory 1 has been halved due to the replacement by the instruction . The third command causes the conventional switch matrices 5 and 6 to control the control mechanism shown in the circuit example shown in FIG. This can be achieved by preparing.

51, 52, and 53 are portions of the switch matrix 5 that correspond to signals. The following is a step-by-step explanation.

First, in the process shown in FIG. 3, it is necessary to read A(1), which is the content of the scalar register 2o, according to the instruction decoding result 111, and write this as the first element of the vector register 11. When the instruction is started, the control circuit 100 of the vector register 10 and the control circuit 110 of the vector register 11 clear the read element number and the write element number to O by 121 to 122, respectively. Further, the signal 121 is transmitted to the selector 47
The data in the scalar register 20 is read out for only one cycle, and the signal 147 is output from the switch matrix 6.
is sent to the switch matrix 53 for data.

This data is sent by signal 157 to the vector register 11 known by signal 112, but at this point the write address counter held by 110 remains at the value O when cleared, and is written by 115 as the 0th element. It will be done. At that time, whether writing is possible or not and the address increase for writing the next element is 111.
The delay latch 150 performs an OR operation on the signal 109 synchronized with the scalar register data. 187. Reference numeral 52 denotes a switch matrix for address increment and write permission signals, and each time the write address reaches 110 via 117, the write address increases, and 115 changes the write destination element number.

On the other hand, after the value of the first scalar register is written, the read permission signal 107 for one element starts to be output for the written data of the vector register 10, and the read address counter value in 100 is increased. , by the address line 106,
By controlling the selector 45 and controlling the selector 46 using 113, the elements of the vector register 10 can be read one after another starting from the 0th element.

In this way, the second to Nth elements of the vector register 11 are written. In FIG. 5, 146 is a read data line from another register, and the signal 123 after holding 113 indicates that the target data is selected using the selector 46.Finally, A(N+1 ) is required to be written to the scalar register 20 instead of the vector register 11, but the final data 11 in this instruction processing
A NAND gate 41 and an AND gate 43 are used to inhibit writing to. When the signal 108 indicating processing other than this instruction or the end of instruction processing is not 1', 198
is always 1', and the gate 43 is through. In this embodiment, the scalar register associated with the vector register 11 is handled as if it were to be written unconditionally by the end signal 118 corresponding to the register, but it can be easily inferred that independent processing is also possible for the scalar register alone. can. In the end signal switch matrix 51, 48 is a distributor that specifies the destination by the signal 112, and 49 is an OR gate that ORs the signal 149 from another writing port. In this embodiment, therefore, the distributor always writes “0” to unused write ports.
However, it is generally possible to use a selector configuration using a conversion circuit.

〔Effect of the invention〕

As described above, according to the present invention, several gates such as those shown at 41, 43, and 44 in FIG. , a high-speed inter-element shift function is realized, and the use of scalar registers allows processing while keeping all vector lengths the same. By this, the first
The amount of accesses to the main memory shown in the figure is almost halved, and the high-speed performance of vector registers can be further exploited by:
it is obvious.

[Brief explanation of the drawing]

Fig. 1 is an example of a Fortran program, Fig. 2 is an example of processing according to the prior art, Fig. 3 is an example of instruction specifications constituting the present invention, Fig. 4 is an example of processing according to the present invention, and Fig. 5 is an example of processing according to the present invention. An example of a circuit that achieves this. Part 1 Diagram 2

Claims (1)

[Claims] 1. It has a plurality of vector data and one or more scalar registers, and when vector data is stored redundantly in two vector registers so that the element numbers differ by 1, the element number is 1. A vector register whose element number is 1 earlier than a scalar register that holds data to be stored in the first part of the vector register whose element number is 1 earlier. A vector processing device having instruction means for obtaining instructions. 2. The vector processing device according to claim 1, wherein a normal arithmetic unit is not used in the instruction processing described above.