JPH0456352B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In order to enable a vector register to be used by multiple scalar units without reducing throughput, the vector register is divided into multiple units to multiply the number of registers that can be specified. increase to

[Industrial application field]

The present invention relates to an information processing device,
In particular, the present invention relates to a method for configuring vector registers shared by a plurality of scalar units in a multiprocessor system.

[Conventional technology]

In recent supercomputers, speed has been increased by adopting a multiprocessor system configuration, and furthermore, a vector calculation mechanism using dedicated hardware has been installed to perform high-speed vector calculation processing.

By the way, in a conventional multiprocessor system equipped with a vector operation mechanism, one vector unit VU is used for multiple scalar units SU.
In some cases, only one scalar unit SU is provided, and the vector register VR of the VU is shared by a plurality of scalar units SU.

FIG. 3 is a block diagram showing an example of such a system. In the figure, 30 is a vector unit VU, 31 is a vector register VR, 32 is a scalar unit SU-0, and 33 is a scalar unit SU.
-1 and 34 represent a storage control unit MCU, and 35 represents a main storage unit MSU.

FIG. 4 shows an example of the configuration of the vector register VR in a single system.

In the figure, 40 is a vector register VR, 4
1 is an address input terminal, 42 is a selector, 43 is an address register array having a shift register configuration, 43
0 to 437 are address registers, 44 is +1
Adder 45 represents an addition control signal input terminal.

The vector register VR is composed of eight banks numbered from #0 to #7, two elements of vector data are assigned to each bank, and one bank is accessed every cycle. Therefore, the access throughput is 2 elements/cycle.

Also, there are 256 registers in VR from No. 0 to 255.
16 elements can be specified, and one register contains 16 elements. If you want to use 16 or more elements, access multiple consecutive registers.

When there is an access request to a register with VR, the address of VR (i.e. register number)
is input from the address input terminal 41, and is shifted through the selector 42 to each address register 430 to 437 in the address register array 43, accessing eight banks in order.

When using 16 or more elements, the address is incremented by 1 in the +1 adder 44 by the addition control signal applied from the addition control signal input terminal 45.
The data is controlled to be accessed again starting from bank #0 via the selector 42.

For example, specifying the register at address 0, 20
When using elements of
#7 is accessed, and in the second round, banks #0 and #1 are accessed with address 1.

By the way, all the registers of such vector register VR can be expressed as scalar unit in Figure 3.
If it is possible to specify from both SU-0 and SU-1, a conflict may occur where both SU-0 and SU-1 use the same register. Therefore, in the case of multiple systems, the way VR is used must be restricted to avoid conflicts.

[Problem that the invention attempts to solve]

Several methods can be considered to avoid contention when multiple scalar units share one vector register.

For example, one method is to divide all the registers in a vector register into a plurality of registers and allocate them independently to each scalar unit. but,
This method reduces the number of registers that can be accessed by each scalar unit and is incompatible with software on single processor systems. Furthermore, the access mechanism becomes complicated.

To solve this problem, either increase the amount of vector register hardware (number of registers), or
It would be necessary to reduce the number of elements per bank, and the latter would result in a reduction in access loops.

In this way, in conventional multiprocessor systems, when multiple scalar units share one vector unit, compared to a single processor, more hardware is required and access throughput is reduced. Problems arose, such as a decline in energy consumption.

[Means for solving problems]

The present invention allows vector registers to be specified separately without reducing the number of registers that can be specified for each scalar unit when a plurality of scalar units share them, and also allows the access throughput to remain the same. , means are provided for dividing the bank of vector registers in correspondence with the number of scalar units and allowing access from each divided position.

FIG. 1 is a diagram illustrating the basic configuration of the present invention.

In the figure, reference numeral 10 shows an example of the configuration of a vector register VR in a conventional single processor system for comparison with the present invention. This vector register is specified by an address between 0 and 255.
The 256 registers are composed of 8 banks #0 to #7. Reference numeral 11 designates a vector register VR newly constructed according to the present invention so that it can be shared by two scalar units in the case of a dual processor system.

Since the number of scalar units is 2, the vector register VR11 stores 8 banks as #0.
~#3 and #4~#7, and access can be started for each divided unit.

Therefore, while the number of registers in vector register VR10 was 256, the number of registers in vector register VR11 is substantially doubled to 512. However, the number of elements per register is halved.

Generally, the number of banks of vector register VR is M
For example, by dividing this bank by N, a divisor of M, and making each divided bank accessible from the beginning, the apparent number of registers can be reduced to N.
Can be doubled.

[Effect]

In the example shown in Figure 1, the vector register VR has 8 banks (M=8) and 256 registers.
By dividing the bank into two (N=2), the apparent number of registers is doubled to 512.

Therefore, for example, in a multiprocessor system (dual processor system) with two scalar units, by allocating half of 256 registers to each scalar unit,
As in the case of a single processor system, each scalar unit can specify and process 256 registers without conflict.

In general, if M banks can be divided into N, the number of registers can be increased by N times, so if the number of registers that can be specified in one scalar unit is not changed, then N It can be shared by multiple scalar units.

Further, by dividing the vector register VR into banks, the number of elements in the bank for access by each scalar unit does not change, so the access throughput does not decrease.

Note that bank division reduces the number of elements per register, but by continuously using sequential registers, vector data of arbitrary element length can be handled.

〔Example〕

FIG. 2 shows the main structure of a system according to an embodiment of the present invention. In the figure, 20 is a physical vector register VR with an 8-bank configuration and 256 address positions per bank, 21 is an address input terminal, 22A and 22B are selectors, 2
3 is an address register string of the system register configuration,
230 to 237 are address registers, 24 is a +1 adder, 25 is an addition control signal input terminal, 26
and 27 are virtual vector registers, respectively.
represents VR′.

The banks of vector register VR20 are #0~
It is divided into left and right halves, #3 and #4 to #7, and is connected to bank #0 by selectors 22A and 22B, respectively.
Alternatively, it is controlled so that access can be started from either #4.

As a result, the number of registers that can be accessed by the vector register VR20 is 512, which is twice the number of 256 address locations. Further, in this example, since the access unit for each bank is two elements, one register has a size of eight elements.

This vector register register VR20 is divided into two groups of 256 registers each on the upper and lower registers as shown in the figure, and each of these registers is a virtual vector register.
The association with VR'26 and VR'27 allows them to be shared by two scalar units, such as SU-0 and SU-1 shown in FIG. 3, without register contention.

These virtual registers VR'26 and VR'27
is 8 banks 25 when viewed from the scalar unit.
It appears as a vector register with 6 registers and 8 elements/register configuration.

In this case, the address position of each bank in the vector register VR20 is configured to change by two.

Next, the access mechanism of the vector register VR20 will be explained.

Each link #0 to #7 of vector register VR20
Each address position is specified by an address set in address registers 230 to 237, respectively. The address is input from address input terminal 21 to the corresponding one of address registers 230 and 234 via one of selectors 22A and 22B.

In vector register VR, bank #0~
The register located at #3 is an even numbered register, and the registers located at banks #4 to #7 are odd numbered registers.

When specifying an even numbered register, a path is set to the left side (L) of the selector 22A, the address on the address input terminal 21 is set to the address register 230, and then the address registers 231, 232, 233 are set at a predetermined timing. will be shifted to As a result, one even-numbered register (8 elements) located at the designated address position in banks #0 to #3 of the vector registers has been accessed.

On the other hand, when specifying an odd numbered register, a path is set on the right side (R) of the selector 22B, and the input address is set in the address register 234, then 235, 236, 23
7, and one register (8 elements) located at a designated address position in banks #4 to #7 is accessed.

If the vector length is 8 or more elements, then adjacent registers are concatenated and used.

For example, when connecting an even numbered register to the next odd numbered register, a path is set to the left side (L) of the selector 22B, and the path is set to the left side (L) of the address register 22B.
The address shifted out from 33 is transferred to address register 234.

When connecting an odd numbered register to the next even numbered register, the address shifted and output from the address register 237 is input to the +1 adder 24, and an addition control signal is applied from the addition control signal input terminal 25. Add +1 to the address and at the same time set a path to the right side (R) of the selector 22A and return it to the address register 230. At this time, since the address has increased by 1, in bank #0,
The next address location is accessed.

In this way, data can be accessed by concatenating and using sequential registers of arbitrary veccle length in units of 8 elements. In addition,
The number of elements accessed in each cycle is two.

〔Effect of the invention〕

According to the present invention, it is possible to switch from a single processor system to a multiprocessor system with the same vector register capacity, while reducing the number of usable registers per scalar unit and the access throughput. Therefore, performance degradation can be suppressed and software compatibility can be maintained to a certain extent.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is a diagram showing the configuration of an embodiment of the system according to the present invention, FIG. 3 is a diagram showing an example of the configuration of a conventional computer system to which the present invention is applied, and FIG. The figure is a configuration diagram of a conventional vector register. In FIG. 1, 10... conventional vector register VR, 11... vector register based on the present invention
VR.

Claims (1)

[Scope of Claims] 1. In a vector register interleaved by M banks, where M and N are each integers larger than 2, M address registers correspond to each of the M banks. The M banks and M address registers are each divided into N groups, and each address register in each of the N groups is connected in series to form one shift register. Insert a 2-input selector at each group boundary you see,
A path is selectively set between the first address register in each group and the address input terminal or between the last address register in the immediately preceding group, and the first address register in the first group A +1 adder is provided between the address register and the last address register in the last group to increment the address by 1 according to instructions, and by dividing the M banks into N groups, the number of vector registers is reduced to N. A vector register configuration method characterized in that the number of vector registers that can be specified is apparently multiplied by N by making it possible to start vector register access from an intermediate bank in each group of divided banks. .