JP5673322B2 - Vector processing apparatus, system, and operation method of vector processing apparatus - Google Patents

Description

  The present invention relates to a vector processing device and a system having the vector processing device.

  The vector processing apparatus has a vector register file that stores vector data, which is array-type data, in order to execute a large amount of data with a small number of instructions. The vector register file is partitioned into a plurality of data registers each storing vector data. The data register has a size corresponding to the vector length indicating the size of the data array, and is specified by an operand included in an instruction executed by the vector processing device. For example, when executing the addition instruction, the vector processing apparatus adds a plurality of sets of data stored in two data registers indicated by two operands. In a vector processing device with a variable vector length, the number of data registers and the relative position of the data registers are set according to the vector length (see, for example, Patent Documents 1 and 2).

JP 54-93342 A JP 59-65378 A

  However, the number of data registers that can be allocated depends on the number of bits of the operand, for example, 32 when the operand is 5 bits. For this reason, when the vector length is small, an area that cannot be allocated as a data register occurs in the vector register file. In other words, when the capacity of the vector register file is larger than the product of the maximum number of data registers that can be specified by the operand and the vector length, an area that cannot be used for the operation occurs in the vector register file.

  An object of the present invention is to efficiently use a vector register file even when the vector length is small, and to improve the performance of the vector processing apparatus.

In one aspect of the present invention, a vector processing device includes a vector register file to which a plurality of data registers for storing vector data are allocated, and a maximum that can be specified by an operand included in the vector register file and included in an instruction. A plurality of register sets each having a number of data registers, the size of which changes according to the vector length, and information indicating an effective register set, which is a register set that holds vector data used for vector operations, among the register sets Using the control register to be stored, the decoder that accesses the data register specified by the operand based on the start position of the valid register set that changes according to the vector length, and the vector data from the accessed data register Perform vector operations And an execution unit. In the vector register file, physical register numbers are sequentially assigned to the data storage areas in which vector data is stored, and each register set has the same number as the product of the vector length and the maximum number of data registers. Registers are numbered in the order of physical register numbers, and the data registers in each register set have the same number of data storage areas as the vector length. Logical register numbers are assigned in order of the size of the number, the control register stores the register set number as information, the operand indicates the logical register number, and the physical data storage area at the head of the data register specified by the operand The register number is the product of the logical register number and the vector length. Specified by the maximum number of the value obtained by adding the product of the vector length of the static set number and the data register.

  Even when the vector length is small, the vector register file can be used efficiently by switching the register set, and the performance of the vector processing apparatus can be improved.

1 illustrates an example of a vector processing device according to an embodiment. An example of the specification of the control register file and the allocation of the data storage area of the vector register file shown in FIG. 1 is shown. In the vector processing device shown in FIG. 1, an example of allocation of data storage areas of a vector register file when the vector length is set to “8” is shown. In the vector processing apparatus shown in FIG. 1, an example of allocation of data storage areas of a vector register file when the vector length is set to “16” is shown. In the vector processing apparatus shown in FIG. 1, an example of allocation of data storage areas of a vector register file when the vector length is set to “32” is shown. In the vector processing apparatus shown in FIG. 1, an example of allocation of the data storage area of the vector register file when the vector length is set to “64” is shown. FIG. 3 shows an example of the operation of a register transfer instruction for transferring data between register sets in the vector processing apparatus shown in FIG. In the vector processing apparatus shown in FIG. 1, another example of the operation of a register transfer instruction for transferring data between register sets is shown. The example of the allocation of the data storage area of the vector register file in the vector processing apparatus of another embodiment is shown. FIG. 10 shows an example in which the vector register file shown in FIG. 9 is represented in a matrix. 9 shows an example in which the vector register file VR shown in FIG. 9 is represented in a matrix when the vector length is “16”. 9 shows an example in which the vector register file VR shown in FIG. 9 is represented in a matrix when the vector length is “32”. FIG. 10 shows an example of the operation of a register transfer instruction for transferring data between register sets in the vector processing apparatus having the vector register file shown in FIG. The example of the allocation of the data storage area of the vector register file in the vector processing apparatus of another embodiment is shown. The example of the allocation of the data storage area of the vector register file in the vector processing apparatus of another embodiment is shown. The example of the system by which the vector processing apparatus mentioned above is mounted is shown.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1 shows an example of a vector processing apparatus according to an embodiment. The vector processing apparatus includes an instruction memory 10, an instruction buffer 12, a decoder 14, a register file group 16, an execution pipeline 18, and a data memory 20. Note that the instruction memory 10, the instruction buffer 12, and the data memory 20 may be arranged outside the vector processing device.

  The instruction memory 10 stores a program in which instructions executed by the vector processing device are described. The instruction buffer 12 temporarily stores instructions prefetched from the instruction memory 10.

  The decoder 14 sequentially decodes the instructions stored in the instruction buffer 12 and outputs the decoded instruction code to the execution pipeline 18. The decoder 14 recognizes a register to be accessed based on the decoded operand, the vector length VL and the register set number REGSET stored in the control register of the control register file VCR, and accesses the recognized register. The access request is output to the register file group 16. The vector length VL and the register set number REGSET will be described with reference to FIG.

  The register file group 16 includes a vector register file VR, a control register file VCR, and the like. The vector register file VR stores vector data (hereinafter also simply referred to as data) used for vector operations. The control register file VCR stores control information and the like necessary for allocation of data areas stored in the vector register file VR.

  The vector register file VR and the control register file VCR output the data stored in the register designated by the access request from the decoder 14 to the execution pipeline 18. Further, the vector register file VR and the control register file VCR store data from the execution pipeline 18 in a register specified by an access request from the decoder 14. Examples of the vector register file VR and the control register file VCR are shown in FIG.

  The execution pipeline 18 has a plurality of arithmetic units that can operate in parallel. The execution pipeline 18 is an example of an execution unit that executes vector operations using vector data from the logical register REGL (FIG. 2) in the vector register file VR accessed by the decoder 14. For example, when the instruction decoded by the decoder 14 is an operation instruction such as an addition instruction, the execution pipeline 18 calculates vector data output from the vector register file VR and writes the operation result to the vector register file VR. The execution pipeline 18 transfers data between the register file group 16 and the data memory 20 when the instruction decoded by the decoder 14 is a transfer instruction such as a load instruction or a store instruction. For example, in the load instruction, vector data used for an operation stored in the data memory 20 is written into the vector register file VR. For example, in the store instruction, vector data obtained by calculation and stored in the vector register file VR is written into the data memory 20.

  FIG. 2 shows an example of the specification of the control register file VCR shown in FIG. 1 and the allocation of the data storage area of the vector register file VR. The control register file VCR has control registers for storing information indicating the vector length VL and the register set number REGSET. The vector length VL indicates the number of data (the number of operations) on which an operation is executed in response to one instruction. In this example, the vector length VL is set to one of “8”, “16”, “32”, and “64”. By making the vector length VL variable, the vector operation can be executed by efficiently using the vector register file VR according to the size of the data array.

  The register set number REGSET indicates the position of the register set REGS used in the operation among the register sets REGS assigned in the vector register file VR. In FIG. 2, the register set REGS designated by the register set number REGSET is indicated by “<numerical value>”. For example, when the register set number REGSET is “2”, the register set REGS of “<2>” indicated by a thick frame in FIG. 2 is selected and can be accessed. The accessible register set REGS indicated by a thick frame is an effective register set that holds vector data used for vector operations. The valid register set is specified by a register set number REGSET set in the control register file VCR.

For example, the vector length VL and the register set number REGSET are set in the control register file VCR by the execution pipeline 18 executing the load immediate control instruction shown in Expression (1). An operand vcr in equation (1) indicates the position (logical number) of each control register in the control register file VCR. For example, “2” in the operand vcr indicates a register for the vector length VL, and “6” in the operand vcr indicates a register for the register set number REGSET. Operand #i indicates an immediate value. For example, when “i” is “16”, “16” is set in the control register specified by the operand vcr, and when “i” is “1”, “1” is set in the control register specified by the operand vcr. Is set.
lic vcr, #i (1)
The vector register file VR has, for example, 2048 (2048 words) data storage areas that can store vector data. Each data storage area is assigned a physical register number (0 to 2047) in order. The vector register file VR is partitioned into a plurality of register sets REGS having the same storage capacity according to the vector length VL. The top physical register set number shown in FIG. 2 is the physical register number of the top data storage area in the register set REGS specified by the register set number REGSET. Each register set REGS is given a register set number REGSET (<0>-<n>) in the order of the physical register number.

  One register set REGS is partitioned into 32 logical registers REGL. The logical register REGL is an example of a data register specified by an operand included in an instruction. Each logical register REGL has the same number of data storage areas as the vector length VL, and stores one vector data. Therefore, the number of data storage areas allocated to each register set REGS is “VL × 32”. The top physical register number shown in FIG. 2 is the top physical register number of the logical register REGL specified by the operand (vr0, vr1, vr2, etc.) for specifying the data array in the instruction. In FIG. 2, the position of the logical register REGL designated by the operand is indicated by “(numerical value)”. For example, when the operand vr0 is “2”, the logical register REGL (2) in the valid register set REGS <2> shown in FIG.

  The logical registers REGL are assigned logical register numbers (0 to 31) in the order of the physical register numbers. The number of logical registers REGL in each register set REGS (32 in this example) is determined depending on the number of bits of an operand for designating a data array included in an instruction decoded by the decoder 14. In this example, the operand is 5 bits, and the maximum number of logical registers REGL that can be specified by the operand is 32. The number of logical registers REGL assigned to each register set REGS is 16 when the operand is 4 bits, and 64 when the operand is 6 bits.

The number (n + 1) of register sets REGS assigned to the vector register file VR is obtained by Expression (2). Here, the total number of physical registers indicates the number of data storage areas allocated to the vector register file VR (in this example, 2048). The total number of logical registers is the maximum number of logical registers REGL that can be specified by the operand, and is “32” in this example.
(Number of register sets REGS) = (Total number of physical registers) / ((Total number of logical registers) × VL) (2)
The decoder 14 shown in FIG. 1 obtains the top physical register set number from Expression (3), and obtains the top physical register number from Expression (4). The head physical register set number is a physical register number indicating the start position of an effective register set obtained in advance based on the vector length VL and the register set number REGSET stored in the control register. The total number of logical registers depends on the instruction set (number of operand bits) of the vector processing device, and is a value determined when the vector processing device is designed. The total number of logical registers is held in the decoder 14 in advance. Using the operand (logical register number) included in the instruction, the decoder 14 obtains the top physical register number based on Expression (4) and outputs it to the register file group 16 as an access request.
(Start physical register set number) = REGSET x (total number of logical registers) x VL (3)
(Start physical register number) = (Logical register number) x VL + (Start physical register set number) (4)
For example, when the execution pipeline 18 executes an addition instruction (an example of a vector operation) shown in Expression (5), the decoder 14 uses the logical register numbers set in the operands vr0, vr1, and vr2 based on the logical register numbers. The head physical register number is obtained from (4) and output to the vector register file VR. The vector register file VR outputs the vector data stored in the logical register REGL indicated by the head physical register number indicated by the decoder 14, or stores the vector data in the logical register REGL indicated by the head physical register number. The execution pipeline 18 uses the vector data output from the vector register file VR to execute the addition operation for the number of times indicated by the vector length VL. In the addition instruction, addition of data stored in the logical register REGL indicated by the operands vr0 and vr1 and storage of the addition result in the logical register REGL indicated by the operand vr2 are executed a number of times corresponding to the vector length VL. .
vadd vr0, vr1, vr2 (5)
FIG. 3 shows an example of allocation of the data storage area of the vector register file VR when the vector length VL is set to “8” in the vector processing apparatus shown in FIG. The assignment shown in FIG. 3 is used when the vector length VL of the data array handled by the vector processing apparatus is smaller than “8”. When the vector length VL is “8”, each register set REGS has 256 (8 × 32) data storage areas. For this reason, the vector register file VR having 2048 data storage areas is partitioned into eight register sets REGS <0>-<7> each having 32 logical registers REGL. Each logical register REGL has eight data storage areas.

  For example, when the register set number REGSET is set to “3”, 32 logical registers REGL (0)-(31) included in the valid register set REGS <3> can be specified by the program. When the values of the operands vr0, vr1, and vr2 shown in Expression (5) are “2”, “6”, and “8”, the contents of the logical registers REGL (2) and (6) are added and the result of the addition Storage in the logical register REGL (8) is executed a number of times corresponding to the vector length VL. By setting the value of the register set number REGSET from “0” to “7”, all data storage areas in the vector register file VR can be accessed.

  FIG. 4 shows an example of allocation of the data storage area of the vector register file VR when the vector length VL is set to “16” in the vector processing apparatus shown in FIG. The assignment shown in FIG. 4 is used when the vector length VL of the data array handled by the vector processing apparatus is “9” to “16”. When the vector length VL is “16”, each register set REGS has 512 (16 × 32) data storage areas. For this reason, the vector register file VR having 2048 data storage areas is partitioned into four register sets REGS <0>-<3> each having 32 logical registers REGL. Each logical register REGL has 16 data storage areas.

  For example, when the register set number REGSET is set to “1”, 32 logical registers REGL (0)-(31) included in the valid register set REGS <1> can be specified by the program. The operation when the values of the operands vr0, vr1, and vr2 shown in Expression (5) are “2”, “6”, and “8” are different in the number of additions corresponding to the top physical register number and the vector length VL. Except for, the same as FIG. Also in FIG. 4, by setting the value of the register set number REGSET from “0” to “3”, all data storage areas in the vector register file VR can be accessed.

  FIG. 5 shows an example of allocation of the data storage area of the vector register file VR when the vector length VL is set to “32” in the vector processing apparatus shown in FIG. The assignment shown in FIG. 5 is used when the vector length VL of the data array handled by the vector processing apparatus is “17” to “32”. When the vector length VL is “32”, each register set REGS has 1024 (32 × 32) data storage areas. Therefore, the vector register file VR having 2048 data storage areas is partitioned into two register sets REGS <0>-<1> each having 32 logical registers REGL. Each logical register REGL has 32 data storage areas.

  For example, when the register set number REGSET is set to “1”, 32 logical registers REGL (0)-(31) included in the valid register set REGS <1> can be specified by the program. The operation when the values of the operands vr0, vr1, and vr2 shown in Expression (5) are “2”, “6”, and “8” are different in the number of additions corresponding to the top physical register number and the vector length VL. Except for, the same as FIG. Also in FIG. 5, by setting the value of the register set number REGSET to either “0” or “1”, all data storage areas in the vector register file VR can be accessed.

  FIG. 6 shows an example of allocation of the data storage area of the vector register file VR when the vector length VL is set to “64” in the vector processing apparatus shown in FIG. The assignment shown in FIG. 6 is used when the vector length VL of the data array handled by the vector processing device is “33” to “64”. When the vector length VL is “64”, one register set REGS <0> having 2048 (64 × 32) data storage areas and 32 logical registers REGL is allocated. Each logical register REGL has 64 data storage areas.

  The operation when the values of the operands vr0, vr1, and vr2 shown in Expression (5) are “2”, “6”, and “8” are different in the number of additions corresponding to the top physical register number and the vector length VL. Except for, the same as FIG. In FIG. 6, the value of the register set number REGSET is always set to “0”. At this time, all data storage areas in the vector register file VR can be accessed.

  FIG. 7 shows an example of the operation of a register transfer instruction for transferring data between register sets REGS in the vector processing apparatus shown in FIG. For example, the vector length VL is set to “16”.

  When one of the register sets REGS is designated by the register set number REGSET set in the control register file VCR, the decoder 14 shown in FIG. 1 cannot access a data storage area other than the designated register set REGS. Therefore, data transfer between the register sets REGS needs to be performed while temporarily holding the data in the data memory 20 shown in FIG. 1 and switching the register set number REGSET. In other words, two data transfer instructions and at least one load immediate control instruction (formula (1)) must be executed, which is inefficient.

On the other hand, since the vector processing apparatus of this embodiment has the register transfer instruction movset1 shown in Expression (6), the designated register can be designated by a minimum instruction without switching the register set number REGSET. Data can be transferred to a register set REGS other than the set REGS.
movset1 vr0, regset1, regset2 (6)
In Expression (6), the operand regset1 indicates the number (position) of the transfer source register set REGS, and the operand regset2 indicates the number (position) of the transfer destination register set REGS. The operand vr0 indicates a logical register number common to the transfer source and transfer destination register sets REGS. With the register transfer instruction movset1 shown in Expression (6), data can be transferred to the logical register REGL having the same number between different register file sets.

  For example, when the values of the operands vr0, regset1, and regset2 shown in Expression (6) are “6”, “1”, and “0”, they are stored in the logical register REGL (6) of the register set REGS <1>. Data is transferred to the logical register REGL (6) of the register set REGS <0>. The transfer source data may be erased (data movement) or may be left (data copy).

In response to the register transfer instruction movset1, the decoder 14 obtains the top physical register number of the transfer source logical register REGL by Expression (7), and obtains the start physical register number of the transfer source logical register REGL by Expression (8). The obtained head physical register number is output to the vector register file VR as an access request. In response to the register transfer instruction movset1, the execution pipeline 18 reads the vector data stored in the logical register REGL specified by the operand vr0 in the register set REGS specified by the operand regset1, and is specified by the operand regset2. Transfer to the logical register REGL specified by the operand vr0 in the register set REGS.
(Start physical register number of transfer source logical register REGL) = vr0 × VL + regset1 × (total number of logical registers) × VL (7)
(Start physical register number of transfer destination logical register REGL) = vr0 × VL + regset2 × (total number of logical registers) × VL (8)
FIG. 8 shows another example of the operation of the register transfer instruction for transferring data between the register sets REGS in the vector processing apparatus shown in FIG. For example, the vector length VL is set to “16”.

In FIG. 8, data is transferred from an arbitrary logical register REGL of the transfer source register set REGS to an arbitrary logical register REGL of the transfer destination register set REGS. For this reason, in the register transfer instruction movset2 shown in Expression (9), an operand vr1 for specifying the transfer source logical register number and an operand vr2 for specifying the transfer destination logical register number are required. The meanings of the operands regset1 and regset2 are the same as in equation (6).
movset2 vr1, vr2, regset1, regset2 (9)
For example, in FIG. 8, when the values of the operands vr1, vr2, regset1, and regset2 shown in Expression (9) are “5”, “8”, “1”, and “2”, the logic of the register set REGS <1> The data stored in the register REGL (5) is transferred to the logic register REGL (8) of the register set REGS <2>. The transfer source data may be erased (data movement) or may be left (data copy).

  In response to the register transfer instruction movset2, the decoder 14 obtains the top physical register number of the transfer source logical register REGL by Expression (10), and obtains the start physical register number of the transfer source logical register REGL by Expression (11). . In response to the register transfer instruction movset2, the execution pipeline 18 reads the vector data stored in the logical register REGL specified by the operand vr1 in the register set REGS specified by the operand regset1, and is specified by the operand regset2. Transfer to the logical register REGL specified by the operand vr2 in the register set REGS.

(Start physical register number of transfer source logical register REGL) = vr1 × VL + regset1 × (total number of logical registers) × VL (10)
(Start physical register number of transfer destination logical register REGL) = vr2 × VL + regset2 × (total number of logical registers) × VL (11)
Note that the vector processing device may include the register transfer instruction movset1 shown in Expression (6) in the instruction set, and may include the register transfer instruction movset2 shown in Expression (9) in the instruction set. Both register transfer instructions movset1 and movset2 shown in (9) may be included in the instruction set.

  As described above, in this embodiment, the register set number REGSET can be switched by the control register, so that all data storage areas of the vector register file VR can be accessed without depending on the vector length VL. Further, all data storage areas of the vector register file VR can be accessed without depending on the number of bits of the operand that designates the logical register REGL. In particular, all data storage areas of the vector register file VR can be accessed in a vector processing device in which the size and start position of the register set REGS changes according to the vector length VL. As a result, the vector register file VR can be used efficiently, and the performance of the vector processing device can be improved.

  By assigning register set numbers to a plurality of register sets REGS having the same storage capacity in the order of the physical register numbers, the position (physical register number) of the logical register REGL to be accessed in the effective register set can be simplified. It is obtained using an equation. As a result, the logic of the decoder 14 for obtaining the physical register number can be simplified.

  By adding the register transfer instruction to the instruction set, data transfer between the register sets REGS can be executed with a small number of instructions, and the performance of the vector processing apparatus can be improved.

  FIG. 9 shows an example of allocation of the data storage area of the vector register file VR in the vector processing apparatus of another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The configuration of the vector processing apparatus is the same as that in FIG. 1 except that the operations of the decoder 14 and the execution pipeline 18 are different. The specification of the control register file VCR is the same as that in FIG.

  In this embodiment, the allocation specification of the data storage area of the vector register file VR is different from FIG. Similar to FIG. 2, the vector register file VR has, for example, 2048 (2048 words) data storage areas. However, the vector register file VR is partitioned into 32 logical registers REGL having the same number of data storage areas. That is, the vector register file VR is partitioned into logical registers REGL whose size and physical register number are fixed regardless of the vector length VL. The logical register REGL is an example of a data register specified by an operand included in an instruction.

  The maximum number of logical registers REGL is determined depending on the number of bits of the operand for designating the data array included in the instruction. That is, also in this example, the number of bits of the operand for designating the data array is “5”. Each logical register REGL has a data storage area in which the same number of physical register numbers as the maximum value VLmax (for example, 64) of the vector length VL continues. The number of data storage areas allocated to each logical register REGL is fixed independently of the vector length VL. The logical registers REGL are assigned logical register numbers (0) to (31) in order of the physical register numbers.

  The shaded portion in FIG. 9 shows a data storage area that can be accessed when the vector length VL is set to “8” and the register set number REGSET is set to “2”. Each shaded portion has the same number (8) of data storage areas as the vector length VL. A set of shaded portions corresponds to the register set REGS <1> indicated by a thick frame in FIG. The register set REGS <1> is an effective register set that holds vector data used for vector operations. In this embodiment, each register set REGS is formed by a set including a part of each of the logical registers REGL, and the register set numbers are given in the order of the size of the physical register numbers. In other words, each logical register REGL is equally allocated to all the register sets REGS.

The head physical register number shown in FIG. 9 is the physical address of the head data storage area in which the data array to be calculated is stored in the logical register REGL specified by the operand (vr0, vr1, vr2, etc.) included in the instruction. Register number. The decoder 14 obtains the head physical register number from Expression (12). Note that the maximum value VLmax of the vector length VL is a value determined at the time of designing the vector processing apparatus, and is held in the decoder 14 in advance.
(Start physical register number) = (Logical register number) x VLmax + REGSET x VL (12)
For example, the decoder 14 obtains the head physical register number from the equation (12) based on the logical register number set in each operand vr0, vr1, and vr2 included in the addition instruction shown in the equation (5), and calculates the vector Output to register file VR. The vector register file VR outputs the vector data stored in the logical register REGL indicated by the head physical register number indicated by the decoder 14, or stores the vector data in the logical register REGL indicated by the head physical register number. The execution pipeline 18 uses the vector data output from the vector register file VR to execute the addition operation for the number of times indicated by the vector length VL.

  FIG. 10 shows an example in which the vector register file VR shown in FIG. 9 is represented in a matrix. As in FIG. 9, the vector length VL is set to “8”, and the register set number REGSET is set to “2”. The shaded portion corresponds to the shaded portion in FIG. A vertically long frame shown in FIG. 10 indicates a register set REGS specified by the register set number REGSET. In FIG. 10, the register set REGS designated by the register set number REGSET is indicated by “<numerical value>”.

  The number of register sets REGS assigned to the vector register file VR is obtained by the above-described equation (2). That is, when the vector length VL is “8”, the vector register file VR is partitioned into eight register sets REGS <0>-<7>. In the logical registers REGL (0)-(31), the portions included in each register set REGS are relatively at the same position from the top of the logical register REGL, have the same number as the vector length VL, and have consecutive physical register numbers. A data storage area is provided.

  For example, in the addition instruction, the values of the operands vr0, vr1, and vr2 shown in Expression (5) are “2”, “6”, and “8”. At this time, the addition of the contents of the data storage area corresponding to the register set REGS <1> of the logical registers REGL (2) and (6) and the register set REGS <1> of the logical register REGL (8) as a result of the addition Storage in the data storage area to be performed is executed a number of times corresponding to the vector length VL. In other words, the shaded area specified by the operands vr0, vr1, and vr2 is accessed as a partial logical register REGL.

  Also in this embodiment, by setting the value of the register set number REGSET from “0” to “7”, all data storage areas in the vector register file VR can be accessed.

  FIG. 11 shows an example in which the vector register file VR shown in FIG. 9 is represented in a matrix when the vector length VL is “16”. Detailed description of the same elements as those in FIG. 10 is omitted. When the vector length VL is “16”, the vector register file VR is partitioned into four register sets REGS <0>-<3> according to Expression (2). The addition operation executed in response to the addition instruction is the same as that in FIG. 10 except that the number of data to be added (number of additions) is different.

  FIG. 12 shows an example in which the vector register file VR shown in FIG. 9 is represented in a matrix when the vector length VL is “32”. Detailed description of the same elements as those in FIG. 10 is omitted. When the vector length VL is “32”, the vector register file VR is partitioned into two register sets REGS <0>-<1> according to the equation (2). The addition operation executed in response to the addition instruction is the same as that in FIG. 10 except that the number of data to be added (number of additions) is different. The allocation of the data storage area of the vector register file VR when the vector length VL is “64” is the same as in FIG.

  FIG. 13 shows an example of the operation of a register transfer instruction for transferring data between register sets REGS in the vector processing apparatus having the vector register file VR shown in FIG.

  Data storage corresponding to the register set REGS <1> of the logical register REGL (6) when the values of the operands vr0, regset1, and regset2 shown in Expression (6) are “6”, “1”, and “0”. The data stored in the area is transferred to the data storage area corresponding to the register set REGS <0> of the logical register REGL (6). On the other hand, when the values of the operands vr1, vr2, regset1, and regset2 shown in the equation (9) are “3”, “10”, “1”, and “2”, the register set REGS of the logical register REGL (3). The data stored in the data storage area corresponding to <1> is transferred to the data storage area corresponding to the register set REGS <2> of the logical register REGL (10).

  The decoder 14 shown in FIG. 1 uses the expression (12) when executing the register transfer instruction movset1 or movset2, and uses the beginning physical register number of the transfer source data storage area and the start physical register number of the transfer destination data storage area. Is output to the vector register file VR. The vector register file VR outputs the vector data stored in the logical register REGL indicated by the head physical register number indicated by the decoder 14, or stores the vector data in the logical register REGL indicated by the head physical register number. The execution pipeline 18 uses the vector data output from the vector register file VR to execute the addition operation for the number of times indicated by the vector length VL.

  Note that the vector processing device may include the register transfer instruction movset1 shown in Expression (6) in the instruction set, and may include the register transfer instruction movset2 shown in Expression (9) in the instruction set. Both register transfer instructions movset1 and movset2 shown in (9) may be included in the instruction set.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. In other words, the vector register file VR can be used efficiently even in the vector processing device having the vector register file VR in which the allocation of the size and the physical register number is partitioned into the fixed logical register REGL regardless of the vector length VL. Can improve performance.

  FIG. 14 shows an example of allocation of the data storage area of the vector register file VR in the vector processing apparatus of another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The configuration of the vector processing apparatus is the same as that in FIG. 1 except that the operations of the decoder 14 and the execution pipeline 18 are different.

  In this embodiment, the allocation specification of the data storage area of the vector register file VR is different from that in FIG. The specification of the control register file VCR is the same as that in FIG. 2 except that the set value of the register set number REGSET is different. Similar to FIG. 2, the vector register file VR has, for example, 2048 (2048 words) data storage areas. The register set number REGSET indicates the start position of the register set REGS.

  Each register set REGS specified by the register set number REGSET is partitioned into 32 logical registers REGL as in FIG. Each logical register REGL has a number of data storage areas corresponding to the vector length VL. Therefore, the number of data storage areas allocated to the register set REGS is “VL × 32”. That is, the size of the register set REGS changes depending on the vector length VL.

  For example, when the vector length VL is “8”, the register set number REGSET is set from “0” to “1792”. When the vector length VL is “16”, the register set number REGSET is set from “0” to “1536”. When the vector length VL is “32”, the register set number REGSET is set from “0” to “1024”. When the vector length VL is “64”, the register set number REGSET is set to “0”. The register set number REGSET may be set to an arbitrary start position from “0” to “2047”. In this case, for example, when the final data storage area of the vector register file VR is cyclically connected to the first data storage area, the vector data can be obtained even when the final data storage area is in the middle of the register set REGS. Can be securely held.

The head physical register number is the physical register number of the head data storage area in which the data array to be calculated is stored, as in FIG. For example, the decoder 14 obtains the top physical register number from the equation (13) based on the logical register number set in each operand vr0, vr1, vr2 included in the addition instruction shown in the equation (5), and Output to register file VR. The vector register file VR outputs the vector data stored in the logical register REGL indicated by the head physical register number indicated by the decoder 14, or stores the vector data in the logical register REGL indicated by the head physical register number. The execution pipeline 18 uses the vector data output from the vector register file VR to execute the addition operation for the number of times indicated by the vector length VL.
(Start physical register number) = (Logical register number) x VL + REGSET (13)
As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained.

  FIG. 15 shows an example of allocation of the data storage area of the vector register file VR in the vector processing apparatus of another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The configuration of the vector processing apparatus is the same as that in FIG. 1 except that the operations of the decoder 14 and the execution pipeline 18 are different.

  In this embodiment, the start position of the register set REGS is specified by the product of the register set number REGSET and the vector length VL. In other words, the start position of the register set REGS can be specified in units of vector length VL. When the vector length VL is “8”, the register set number REGSET is set from “0” to “224”. When the vector length VL is “16”, the register set number REGSET is set from “0” to “96”. When the vector length VL is “32”, the register set number REGSET is set from “0” to “32”. When the vector length VL is “64”, the register set number REGSET is set to “0”.

  The register set number REGSET may be set to an arbitrary start position from “0” to “2047”. In this case, for example, when the final data storage area of the vector register file VR is cyclically connected to the first data storage area, the vector data can be obtained even when the final data storage area is in the middle of the register set REGS. Can be securely held.

  The top physical register number is the top physical register number of the data array to be calculated, as in FIG. For example, the decoder 14 obtains the head physical register number from the equation (14) based on the logical register number set in each operand vr0, vr1, vr2 included in the addition instruction shown in the equation (5), and Output to register file VR. The operations of the vector register file VR and the execution pipeline 18 are the same as those in FIG.

(Start physical register number) = (Logical register number) x VL + REGSET x VL (14)
The allocation specification of the vector register file VR is the same as that shown in FIG. 14 except that it is specified by the product of the register set number REGSET and the vector length VL, and the method of obtaining the top physical register number is different. As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained.

  FIG. 16 shows an example of a system in which the vector processing device described above is mounted. For example, the system SYS is a built-in communication device such as a mobile phone, and includes an antenna ANT, a high-frequency circuit RF, an analog-digital converter A / D, a vector processing device VP, a processor PROC, and an input / output unit I / O. ing. FIG. 16 shows functional blocks necessary for receiving data via the antenna ANT. The high-frequency circuit RF and the analog-digital converter A / D are an example of a data generation unit that generates vector data used for vector calculation of the vector processing device. The processor PROC is an example of a data processing unit that executes data processing using data calculated by the vector processing device.

  The high-frequency circuit RF extracts a necessary frequency component from the high-frequency signal received via the antenna ANT and outputs it as a baseband signal to the analog / digital converter A / D. The analog-digital converter A / D converts an analog baseband signal into a digital signal and outputs the digital signal to the vector processing device VP. For example, the digital signal is written in the data memory 20 shown in FIG.

  The vector processing device VP is one of the vector processing devices described above. The vector processing device VP operates as a baseband signal processing device, for example, and executes the above-described vector operation. Then, the vector processing device VP demodulates the digital signal supplied from the analog / digital converter A / D and acquires data included in the signal received by the antenna ANT. For example, the vector processing device VP writes the acquired data into the data memory 20. The vector processing device VP may operate as a coprocessor of a CPU that operates to process a baseband signal. In this case, the system SYS includes a CPU that controls the vector processing device VP operating as a coprocessor.

  The processor PROC is an application processor that executes processing according to the type of data acquired by the vector processing device VP, and processes data calculated by the vector processing device VP held in the data memory 20. For example, the processor PROC executes a decoding process for reproducing audio data and a decoding process for reproducing image data. Note that a plurality of processors PROG that respectively perform audio data decoding processing and image data decoding processing may be formed.

  The input / output unit I / O is a user interface unit such as a display that displays image data decoded by the processor PROC, a speaker that outputs audio data decoded by the processor PROG, an input key, or a camera. The vector processing device VP may be mounted on a functional block for transmitting data via the antenna ANT in the system SYS. At this time, the processor that generates transmission data using data supplied from the input / output unit I / O or the like operates as a data generation unit that generates vector data used for vector calculation of the vector processing device. The digital-analog converter that converts digital transmission data calculated by the vector processing device into an analog signal operates as a data processing unit that performs data processing using the data calculated by the vector processing device.

  By mounting the vector processing device VP of the above-described embodiment in the system SYS, it is possible to execute baseband signal processing while efficiently using all regions of the vector register file VR. As a result, the processing efficiency of the baseband signal can be improved, and the performance of the system SYS can be improved.

The invention described in the above embodiments is organized and disclosed as an appendix.
(Appendix 1)
A vector register file to which a plurality of data registers for storing vector data are allocated, and
A plurality of register sets allocated in the vector register file, each having a maximum number of the data registers that can be specified by an operand included in an instruction, the size of which varies according to the vector length;
Among the register sets, a control register that stores information indicating an effective register set that is a register set that holds vector data used for vector operations;
A decoder for accessing the data register specified by the operand with reference to a start position of the valid register set that changes according to a vector length;
An execution unit that executes a vector operation using vector data from the accessed data register.
(Appendix 2)
In the vector register file, a data storage area in which each vector data is stored is assigned a physical register number in order,
Each of the register sets includes the data storage area having the same number as a product of a vector length and the maximum number of data registers, and the physical register numbers are consecutive, and the register set numbers in order of the physical register numbers Is attached,
The data registers in each register set have the same number of data storage areas as the vector length, and logical register numbers are assigned in order of the physical register numbers,
In the control register, the register set number is stored as the information,
The operand indicates the logical register number;
The physical register number of the first data storage area of the data register specified by the operand is obtained by adding the product of the register set number, the maximum number, and the vector length to the product of the logical register number and the vector length. The vector processing device according to supplementary note 1, wherein the vector processing device is specified by a specified value.
(Appendix 3)
In the vector register file, a data storage area in which each vector data is stored is assigned a physical register number in order,
Each data register has the same number as the maximum value of the vector length, includes the data storage area in which the physical register numbers are continuous, and is given a logical register number in order of the size of the physical register number,
Each register set is formed by a set including a part of each of the data registers, and a register set number is given in order of the size of the physical register number,
The portions included in the set in each of the data registers have the data storage areas that are relatively at the same position, have the same number as the vector length, and have consecutive physical register numbers;
In the control register, the register set number is stored as the information,
The operand indicates the logical register number;
In the data register specified by the operand, the physical register number of the leading data storage area in which vector data for performing vector operation is stored is the product of the logical register number and the maximum vector length. The vector processing device according to appendix 1, wherein the vector processing device is specified by a value obtained by adding a product of a register set number and a vector length.
(Appendix 4)
In the vector register file, a data storage area in which each vector data is stored is assigned a physical register number in order,
Each of the register sets includes the data storage area having the same number as a product of a vector length and the maximum number of data registers, and the physical register numbers are continuous.
The data register in each register set has the same number of data storage areas as the vector length, and logical register numbers are assigned in order of the physical register number size,
In the control register, the register set number is stored as the information,
The operand indicates the logical register number;
The physical register number of the data storage area at the head of the data register specified by the operand is specified by a value obtained by adding the register set number to the product of the logical register number and the vector length. The vector processing device according to attachment 1.
(Appendix 5)
In the vector register file, a data storage area in which each vector data is stored is assigned a physical register number in order,
Each of the register sets includes the data storage area having the same number as a product of a vector length and the maximum number of data registers, and the physical register numbers are continuous.
The data register in each register set has the same number of data storage areas as the vector length, and logical register numbers are assigned in order of the physical register number size,
In the control register, the register set number is stored as the information,
The operand indicates the logical register number;
The physical register number of the data storage area at the head of the data register specified by the operand is specified by a value obtained by adding the product of the register set number and the vector length to the product of the logical register number and the vector length. The vector processing device according to supplementary note 1, wherein:
(Appendix 6)
A first operand indicating a position of the data register in each of the register sets; a second operand designating the transfer source register set; and a third operand designating the transfer destination register set; A register transfer instruction having
In response to the register transfer instruction, the arithmetic unit outputs vector data stored in the data register specified by the first operand in the register set specified by the second operand by the third operand. The vector processing device according to any one of appendix 1 to appendix 5, wherein transfer is performed to the data register designated by the first operand in a designated register set.
(Appendix 7)
The instruction set includes a first operand indicating a position of the data register in the transfer source register set, a second operand indicating a position of the data register in the transfer destination register set, and the transfer source A register transfer instruction having a third operand designating a register set and a fourth operand designating the register set to be transferred;
In response to the register transfer instruction, the arithmetic unit specifies the vector data stored in the register set specified by the third operand specified by the first operand by the fourth operand. 6. The vector processing device according to any one of appendix 1 to appendix 5, wherein the vector register is transferred to the data register specified by the second operand in the register set.
(Appendix 8)
The vector processing device according to any one of appendix 1 to appendix 7,
A data generation unit for generating vector data used for vector operation of the vector processing device;
A data processing unit that executes data processing using data calculated by the vector processing device.
(Appendix 9)
An operation method of a vector processing apparatus having a vector register file to which a plurality of data registers for storing vector data is assigned,
A plurality of register sets each having a maximum number of data registers that can be specified by an operand included in an instruction, and a plurality of register sets whose sizes change according to a vector length are allocated in the vector register file;
Among the register sets, information indicating an effective register set that is a register set that holds vector data used for vector operation is stored in a control register;
With reference to the start position of the valid register set that changes according to the vector length, the data register specified by the operand is accessed,
An operation method of a vector processing device, wherein vector operation is executed using vector data from the data register to be accessed.
(Appendix 10)
In the vector register file, a data storage area in which each vector data is stored is assigned a physical register number in order,
Each of the register sets includes the data storage area having the same number as a product of a vector length and the maximum number of data registers, and the physical register numbers are consecutive, and the register set numbers in order of the physical register numbers Is attached,
The data registers in each register set have the same number of data storage areas as the vector length, and logical register numbers are assigned in order of the physical register numbers,
In the control register, the register set number is stored as the information,
The operand indicates the logical register number;
The physical register number of the first data storage area of the data register specified by the operand is the product of the logical register number and the vector length, and the product of the register set number, the maximum number of the data registers, and the vector length. The operation method of the vector processing apparatus according to appendix 9, wherein the vector processing apparatus is specified by a value obtained by adding.
(Appendix 11)
In the vector register file, a data storage area in which each vector data is stored is assigned a physical register number in order,
Each data register has the same number as the maximum value of the vector length, includes the data storage area in which the physical register numbers are continuous, and is given a logical register number in order of the size of the physical register number,
Each register set is formed by a set including a part of each of the data registers, and a register set number is given in order of the size of the physical register number,
The portions included in the set in each of the data registers have the data storage areas that are relatively at the same position, have the same number as the vector length, and have consecutive physical register numbers;
In the control register, the register set number is stored as the information,
The operand indicates the logical register number;
In the data register specified by the operand, the physical register number of the leading data storage area in which vector data for performing vector operation is stored is the product of the logical register number and the maximum vector length. The operation method of the vector processing device according to appendix 9, characterized by being specified by a value obtained by adding a product of a register set number and a vector length.
(Appendix 12)
In the vector register file, a data storage area in which each vector data is stored is assigned a physical register number in order,
Each of the register sets includes the data storage area having the same number as a product of a vector length and the maximum number of data registers, and the physical register numbers are continuous.
The data register in each register set has the same number of data storage areas as the vector length, and logical register numbers are assigned in order of the physical register number size,
In the control register, the register set number is stored as the information,
The operand indicates the logical register number;
The physical register number of the data storage area at the head of the data register specified by the operand is specified by a value obtained by adding the register set number to the product of the logical register number and the vector length. The operation method of the vector processing device according to attachment 9.
(Appendix 13)
In the vector register file, a data storage area in which each vector data is stored is assigned a physical register number in order,
Each of the register sets includes the data storage area having the same number as a product of a vector length and the maximum number of data registers, and the physical register numbers are continuous.
The data register in each register set has the same number of data storage areas as the vector length, and logical register numbers are assigned in order of the physical register number size,
In the control register, the register set number is stored as the information,
The operand indicates the logical register number;
The physical register number of the data storage area at the head of the data register specified by the operand is specified by a value obtained by adding the product of the register set number and the vector length to the product of the logical register number and the vector length. The operation method of the vector processing device according to appendix 9, wherein:

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and modifications, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

  DESCRIPTION OF SYMBOLS 10 ... Instruction memory; 12 ... Instruction buffer; 14 ... Decoder; 16 ... Register file group; 18 ... Execution pipeline; 20 ... Data memory; A / D ... Analog-to-digital converter; ANT ... Antenna; Section: PROC: Processor; REGL: Logical register; REGS: Register set REGSET: Register set number; RF: High frequency circuit; SYS: System: VCR: Control register file; VL: Vector length; VP: Vector processing unit: VR: Vector Register file

Claims (8)

A vector register file to which a plurality of data registers for storing vector data are allocated, and
A plurality of register sets allocated in the vector register file, each having a maximum number of the data registers that can be specified by an operand included in an instruction, the size of which varies according to the vector length;
Among the register sets, a control register that stores information indicating an effective register set that is a register set that holds vector data used for vector operations;
A decoder for accessing the data register specified by the operand with reference to a start position of the valid register set that changes according to a vector length;
An execution unit that executes vector operation using vector data from the accessed data register;
In the vector register file, a data storage area in which each vector data is stored is assigned a physical register number in order,
Each of the register sets includes the data storage area having the same number as a product of a vector length and the maximum number of data registers, and the physical register numbers are consecutive, and the register set numbers in order of the physical register numbers Is attached,
The data registers in each register set have the same number of data storage areas as the vector length, and logical register numbers are assigned in order of the physical register numbers,
In the control register, the register set number is stored as the information,
The operand indicates the logical register number;
The physical register number of the first data storage area of the data register specified by the operand is the product of the logical register number and the vector length, and the product of the register set number, the maximum number of the data registers , and the vector length. the characteristics and be behenate vector processing apparatus that is specified by the value obtained by adding. A vector register file to which a plurality of data registers for storing vector data are allocated, and
A plurality of register sets allocated in the vector register file, each having a maximum number of the data registers that can be specified by an operand included in an instruction, the size of which varies according to the vector length;
Among the register sets, a control register that stores information indicating an effective register set that is a register set that holds vector data used for vector operations;
A decoder for accessing the data register specified by the operand with reference to a start position of the valid register set that changes according to a vector length;
An execution unit that executes vector operation using vector data from the accessed data register;
In the vector register file, a data storage area in which each vector data is stored is assigned a physical register number in order,
Each data register has the same number as the maximum value of the vector length, includes the data storage area in which the physical register numbers are continuous, and is given a logical register number in order of the size of the physical register number,
Each register set is formed by a set including a part of each of the data registers, and a register set number is given in order of the size of the physical register number,
The portions included in the set in each of the data registers have the data storage areas that are relatively at the same position, have the same number as the vector length, and have consecutive physical register numbers;
In the control register, the register set number is stored as the information,
The operand indicates the logical register number;
In the data register specified by the operand, the physical register number of the leading data storage area in which vector data for performing vector operation is stored is the product of the logical register number and the maximum vector length. features and be behenate vector processing apparatus that is specified by the product of the value obtained by adding the register set number and vector length. A vector register file to which a plurality of data registers for storing vector data are allocated, and
A plurality of register sets allocated in the vector register file, each having a maximum number of the data registers that can be specified by an operand included in an instruction, the size of which varies according to the vector length;
Among the register sets, a control register that stores information indicating an effective register set that is a register set that holds vector data used for vector operations;
A decoder for accessing the data register specified by the operand with reference to a start position of the valid register set that changes according to a vector length;
An execution unit that executes vector operation using vector data from the accessed data register;
In the vector register file, a data storage area in which each vector data is stored is assigned a physical register number in order,
Each of the register sets includes the data storage area having the same number as a product of a vector length and the maximum number of data registers, and the physical register numbers are continuous.
The data register in each register set has the same number of data storage areas as the vector length, and logical register numbers are assigned in order of the physical register number size,
In the control register, the register set number is stored as the information,
The operand indicates the logical register number;
The physical register number of the top data storage area of the data register specified by the operand is specified by a value obtained by adding the register set number to the product of the logical register number and the vector length. behenate vector processing unit. A vector register file to which a plurality of data registers for storing vector data are allocated, and
A plurality of register sets allocated in the vector register file, each having a maximum number of the data registers that can be specified by an operand included in an instruction, the size of which varies according to the vector length;
Among the register sets, a control register that stores information indicating an effective register set that is a register set that holds vector data used for vector operations;
A decoder for accessing the data register specified by the operand with reference to a start position of the valid register set that changes according to a vector length;
An execution unit that executes vector operation using vector data from the accessed data register;
In the vector register file, a data storage area in which each vector data is stored is assigned a physical register number in order,
Each of the register sets includes the data storage area having the same number as a product of a vector length and the maximum number of data registers, and the physical register numbers are continuous.
The data register in each register set has the same number of data storage areas as the vector length, and logical register numbers are assigned in order of the physical register number size,
In the control register, the register set number is stored as the information,
The operand indicates the logical register number;
The physical register number of the data storage area at the head of the data register specified by the operand is specified by a value obtained by adding the product of the register set number and the vector length to the product of the logical register number and the vector length. Rukoto features and be behenate vector processing apparatus. A vector register file to which a plurality of data registers for storing vector data are allocated, and
A plurality of register sets allocated in the vector register file, each having a maximum number of the data registers that can be specified by an operand included in an instruction, the size of which varies according to the vector length;
Among the register sets, a control register that stores information indicating an effective register set that is a register set that holds vector data used for vector operations;
A decoder for accessing the data register specified by the operand with reference to a start position of the valid register set that changes according to a vector length;
An execution unit that executes vector operation using vector data from the accessed data register;
A first operand indicating a position of the data register in each of the register sets; a second operand designating the transfer source register set; and a third operand designating the transfer destination register set; A register transfer instruction having
The execution unit, in response to said register transfer instruction, the vector data stored in said data register specified by the first operand in the register set specified by the second operand, the third operand features and be behenate vector processing apparatus to transfer the data register specified by the first operand in the register set specified by the. A vector register file to which a plurality of data registers for storing vector data are allocated, and
A plurality of register sets allocated in the vector register file, each having a maximum number of the data registers that can be specified by an operand included in an instruction, the size of which varies according to the vector length;
Among the register sets, a control register that stores information indicating an effective register set that is a register set that holds vector data used for vector operations;
A decoder for accessing the data register specified by the operand with reference to a start position of the valid register set that changes according to a vector length;
An execution unit that executes vector operation using vector data from the accessed data register;
The instruction set includes a first operand indicating a position of the data register in the transfer source register set, a second operand indicating a position of the data register in the transfer destination register set, and the transfer source A register transfer instruction having a third operand designating a register set and a fourth operand designating the register set to be transferred;
The execution unit, in response to said register transfer instruction, the vector data stored in said data register specified by the first operand in the register set specified by the third operand, said fourth operand features and be behenate vector processing apparatus to transfer the data register specified by the second operand in the register set specified by the. The vector processing device according to any one of claims 1 to 6 ,
A data generation unit for generating vector data used for vector operation of the vector processing device;
A data processing unit that executes data processing using data calculated by the vector processing device. An operation method of a vector processing apparatus having a vector register file to which a plurality of data registers for storing vector data is assigned,
A plurality of register sets each having a maximum number of data registers that can be specified by an operand included in an instruction, and a plurality of register sets whose sizes change according to a vector length are allocated in the vector register file;
Among the register sets, information indicating an effective register set that is a register set that holds vector data used for vector operation is stored in a control register;
With reference to the start position of the valid register set that changes according to the vector length, the data register specified by the operand is accessed,
Performing vector operations using vector data from the data register to be accessed ;
A first operand indicating a position of the data register in each of the register sets; a second operand designating the transfer source register set; and a third operand designating the transfer destination register set; A register transfer instruction having
In response to the register transfer instruction, the vector data stored in the data register specified by the first operand in the register set specified by the second operand is specified by the third operand. A method of operating a vector processing device, comprising: transferring to the data register specified by the first operand in a register set .

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