JPS6113267B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer control circuit for a multi-computer bus coupling system, and more particularly to a data transfer device suitable for a load sharing computer control system that requires high-speed transfer of input/output data.

The conventional method is shown in FIG. The entire system consists of a transfer control circuit 1, a data shared memory 4, a unit driver 10, a P ^I /O5, a bus 9, and a CPU 6. The CPU 6 accesses the data shared memory 4 instead of the P ^I /O5, and This is done completely independently of data transfer. Each CPU 6 accesses its own data shared memory 4, so even though it is a multi-computer system that shares P ^I /O,
Since there is no CPU queue, the processing performance of each CPU 6 can be improved. On the other hand, the data freshness of the data shared memory 4 depends on the data transfer speed of the bus 9. In this conventional method, based on the clock generated by the oscillation circuit 2, the address counter 3
outputs address 7 while updating it at a constant cycle. If this address 7 corresponds to an access input, the corresponding P ^I /O 5 outputs the access input data to the data bus 8 . Other P ^I /O5 do nothing. All data shared memories 4 internally store this process input data. On the other hand, when address 7 corresponds to a process output, the corresponding P ^I /O5 receives output data from data bus 8 and outputs it to the process. other P
^I /O5 does nothing.

In the conventional method, the data freshness of the data shared memory 4, that is, the transfer time T of all data, is 1
The product of the time t required for one data transfer and the total number of input/output data N, that is, T=t×N. In order to increase the speed in this method, it is necessary to reduce the time t for transferring one data, but there is a limit value to the transfer time, and in the conventional method,
There is a drawback that the transfer time T for all data is not shortened.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bus coupling system that is inexpensive, easy to implement, and performs data transfer at high speed.

A feature of the present invention is that although the individual transfer speeds are the same as conventional ones, by transferring input and output simultaneously as a means of effectively using P ^I / O, the overall transfer speed can be doubled. It is in the point that I made it.

Embodiments of the present invention will be described below with reference to FIGS. 2 and 3. The overall structure includes a data shared memory 11, an address/input data bus 15, and an output data bus 1.
6, the transfer control circuit 21, the P ^I /O unit 18, and the inside of the data shared memory 11.
Address register 23, address/input data switching circuit 12, input data RAM 13, output data
The transfer control circuit 21 is composed of a RAM 14, and is composed of an oscillation circuit 2, an address counter 3, and an address upper adder 22. Also, P ^I /
The inside of the O unit 18 includes an address/input data switching circuit 12, an address register 23, and a P ^I /O
It is made up of circuits.

The operation will be explained below. As shown in FIG. 3, address/input data bus 15 operates alternately as an address and input data bus. The switching is performed using an address/input data bus switching signal 16 that is an output of the transfer control circuit 21. P ^I /
For the address of O, separate the input address and output address, input (000) ₁₆ ~ (7FF) ₁₆ , (800) ₁₆ ~
(FFF) ₁₆ is assigned to the output. Also, P ^I /
The O unit 18 and the P ^I /O unit 19 divide these addresses into halves, and the P ^I /O unit 18 has inputs of (000) ₁₆ to (3FF) ₁₆ and inputs of (800) ₁₆ to
(BFF) Implements ₁₆ outputs and 19 P ^I /O units.
has inputs of (400) ₁₆ ~ (7FF) ₁₆ and (C00) ₁₆ ~
(FFF) ₁₆ outputs are implemented. In addition, the transfer control circuit 21 uses the lower 8 bits of the 12 bits output from the address counter 3 as a common input/output address, the higher 4 bits as the upper bits of the input address, and adds the address upper adder 22 ( C) Using the result of adding ₁₆ as the upper bit of the output address, the address/input data bus 15 is
A total of 16 bits, including the above 8 bits, 4 bits, and 4 bits, are output. In this way, the input address and output address are output using a small number of bits. Here, (C) ₁₆ is added and the upper bits of the output address are set because the P ^I /
This is to operate O.

First, the transfer control circuit 21 sets the address/input data switching signal 16 to the address side, and sets the address/input data switching signal 16 to the address side.
The address is output to the input data bus 15. As a result, addresses are set in the data shared memory 11 and the address registers 23 of the P ^I /O units 18 and 19. Next, the transfer control circuit 21
sets the address/input data switching signal 16 to the input data side. As a result, the data shared memory 11
Then, the P ^I /O units 18 and 19 start transferring input/output data. The P ^I /O unit 18 outputs the input data at address (000) ₁₆ to the address/input data bus 15, and outputs the input data at address (000) 16 to the data shared memory 11.
extracts the output data at address (C00) ₁₆ from the output data RAM 14 and outputs it to the output data bus 17. Next, the P ^I /O unit 19 receives this output data and outputs (C00) ₁₆ of the P ^I /O circuit 20.
Output from address to process. On the other hand, input data is received by the data shared memory 11 and stored at address (000) ₁₆ of the input data RAM 13. The above is one cycle, and all data transfer is performed by sequentially updating addresses.

According to this embodiment, since input data and output data are transferred simultaneously within one cycle, the transfer time T for all data is the product of the time t and half the number N of input/output data in one cycle. In other words, T=t×N/2, and it is possible to transfer at twice the speed of the conventional method.

According to the present invention, a transfer speed twice that of the conventional method can be easily achieved at low cost.

[Brief explanation of the drawing]

FIG. 1 is a conventional block diagram, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a time chart of FIG. 6...CPU, 11...Data shared memory, 1
5... Address/input data bus, 17... Output data bus, 18... P ^I /O unit, 20...
...P ^I /O, 21...Transfer control circuit.

Claims (1)

[Claims] 1. In a multicomputer bus coupling system consisting of a bus coupling device that transfers data between multiple CPUs and a shared P ^I /O, both the process input address and the process output address are stored in the upper few bits of the transfer address. Further, a high-speed data transfer device for a bus-coupled system is characterized in that lower addresses are each provided with an address generation circuit that outputs an input/output common address, and is configured to transfer process input data and process output data simultaneously.