JPS5858752B2 - address translation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a virtual computer system realized in a computer system having a virtual storage method,
In particular, the present invention relates to the address translation device.

A virtual memory method is when a processing device accesses data stored in main memory, it uses a virtual address that is determined separately from the address (real address) that indicates the location of the data on the main memory. Indicates the access method.

The virtual storage method has been adopted in many computer systems in recent years, and its details are well known, so further explanation will be omitted.

Note that the correspondence between virtual addresses and real addresses is generally defined by an address translation table managed by software.

Further, converting a virtual address to a real address is referred to as address conversion.

A virtual computer is a real computer that is used for time sharing, and by setting virtual hardware information (control registers, calculation registers, PSW, etc.) to the real hardware in each time slot, one real computer can Each time slot operates as if it were a separate computer.

Therefore, a single computer can run multiple different operating systems at an apparently faster time.

Since the virtual computer method has recently been implemented in several computer systems, a more detailed explanation is not necessary.

In virtual machine systems, virtual storage is generally implemented in a multi-level configuration.

Since this is the basic background of the present invention, it will be explained below.

Each virtual machine has a virtual address and a corresponding real address in order to access data on the main memory, but the real address for a virtual machine is the same as the real address on the main memory. It can't be.

This is because the main storage must appear to each virtual machine as if it were exclusively owned.

Therefore, the real address for each virtual computer is a virtual address for the real computer, and this is converted once again to become a real address on the main storage device.

As described above, in the virtual memory system of the virtual computer system, there are the following three levels of addresses.

(1) Level 1: Real address on main storage (real address for the real computer) (2) Level 2: Virtual address for the real computer (real address for the virtual computer (3)) Level 3: Real address for the virtual computer Although the most basic three-level virtual address has been shown, it is clear that in general, any number of intermediate level addresses can be set between level 1 and level 3.

Therefore, although the present invention can be applied to a general virtual storage system with multi-stage addresses as described later, a specific explanation will be given regarding the three-stage case described above.

By the way, in a virtual memory system having three levels of addresses, the following two types of address translation tables are required.

(1) First address conversion chifur...
...Conversion from level 3 address to level 2 address (2>second address conversion table...)
Conversion from Level 2 Address to Level 1 Address In general, in a virtual storage system having (M+1) levels of addresses, M types of address conversion tables are required.

However, conventionally, when actually accessing data in main memory using a virtual address, the above-mentioned address conversion table cannot be directly referred to by the node-ware of the processing device.

This is because conventional processing devices are designed without being aware of the virtual computer system, and therefore use a new address obtained through one address conversion as a real address.

For this reason, in virtual computer systems, a shadow table, which will be described below, has conventionally been prepared in the main memory at the front of the software and used for reference by the processing unit hardware.

That is, a correspondence table (shadow table) of all level 3 addresses to level 1 addresses is created in advance from the contents of the first and second address translation tables, and this is used for the first and second address translations. It is stored as data on the main memory separately from the table.

When accessing a general main memory, the first and second address translation tables are referred to (by referring to the shadow table, the real address can be obtained by one address translation).

FIG. 1 conceptually shows the relationship between address translation tables for addresses at each level.

A computer system using a virtual memory method generally has an address translation buffer inside the processing device.

This is an associative memory device that stores multiple pairs of virtual addresses and corresponding real addresses, and TLB (Tra
nslation Lookaside Buffer
) etc.

Address translation buffers are a well-known technology and need no explanation.

When a virtual computer system is implemented, the address translation buffer will store level 3 addresses and corresponding level 1 addresses.

When accessing the main memory, if the desired address translation pair is not in the address translation buffer, the desired level 1 address is obtained by referring to the shadow table, and the obtained level 1 address and the original level 3 address are used together with the address. Register in the conversion buffer.

Above, an outline of the conventional technology that implements a virtual memory method in a virtual computer system has been described.

Next, problems with such conventional technology will be explained.

The shadow table is convenient in that there is no need to be aware that the hardware of the processing unit is a virtual computer system, but this has some disadvantages in terms of performance.

The first point is that it takes a lot of time to generate a shadow table.

One virtual space may have thousands to hundreds of pages, which are the minimum unit of address translation.

Referring to the first and second address translation tables for each of them and creating a shadow table will require, on average, 10 steps per page.

Therefore, to generate one shadow table, there are several hundred
A program of several hundred thousand steps must be run.

The second point is that when it becomes necessary to update the information in the address translation table by swapping pages in main memory, not only the first or second address translation table but also the shadow table must be updated. No.

In reality, when it is difficult to partially update a shadow table, the entire shadow table for that space may be invalidated.

In this case, if the space is to be accessed again later, the shadow table must be regenerated, taking a long time as described above.

The third point is that Shadow Teaful itself requires a very large storage capacity.

When several thousand to several hundred pages exist in one space, a small (several hundred) ite storage area is required as a shadow table.

Since the shadow table must be resident in the main memory due to its nature, the shadow table occupies a considerable portion of the main memory.

As mentioned above, Shadow Chiful implements a virtual memory system in a virtual computer system using conventional processing equipment, but it requires a large amount of program running time and main memory to generate and maintain it. It has the disadvantage of consuming space.

Furthermore, although there is likely to be a large amount of data in a set of shadow tables that is never used, the program time and main storage area are equally consumed by these items. time and resources will be wasted.

An object of the present invention is to eliminate the need for the existence of a shadow table, which has the above-mentioned difficulties, by adding new functions to the hardware of a processing device, and to increase the program running time and the effectiveness of the main storage area. It is.

The gist of the present invention is to enable hardware of a processing device to directly refer to the first and second address translation tables.

The content of the present invention will be explained below using an embodiment shown in FIG.

FIG. 2 is a block diagram showing part of a processing device in which the present invention is implemented.

In FIG. 2, the processing device is connected to the main memory 14 on the signal line 1.
is given a virtual address to access.

This is input to the address conversion buffer 2 and converted into a real address.

To be more specific, a virtual address is stored in the address translation buffer 20 section 20, and a plurality of sets of corresponding real addresses are stored in the section 21, and one set is selected and output according to a portion of the virtual address on the signal line 1. be done.

The virtual address output from part 20 of the address translation buffer is compared with virtual address 1 in comparator 3;
If they match, the corresponding real address is applied to the main memory access address line 11 via the gate 4 and selector 10 as a desired real address.

If the results of the comparison in the comparator 3 do not match, the table reference control circuit 5 is activated in order to refer to the address conversion table on the main memory and obtain a desired real address.

When the table reference control circuit 5 is activated, it first refers to the first address translation table.

The register 60 stores the first address of the first address conversion chifur, and the contents of the register 60 are input to the adder 9 via the selector 7.

Also, a part of the virtual address on the signal line 1 is input to the other side of the adder 9, and the result of this addition is given to the line 11 as the first address conversion table address, and the main memory 14
is read out.

The contents of the first address conversion table read from the main memory 14 are level 2 addresses.

This is set in the read data register 13 via the read data line 12 of the main memory 14.

Next, the control circuit 5 reads the second address translation table.

The first address of the second address conversion table is stored in the register 61, and is sent to the adder 9 via the selector 7.
is input.

A part of the level 2 address set in the register 13 is input to the other input of the adder 9, and the result of the power calculation is sent to the main memory access address line via the selector 10 as the second address conversion table address. given to 11.

The desired real address is written in the second address conversion table read from the main memory 14.

This is read out via the main memory read data line 12, set in the data register 13, and from there the signal line 1
4 to the address translation buffer 20 portion 21.

At the same time, the virtual address given to the signal line 1 is also written into the address translation buffer 20 portion 20.

Through the above operations, the desired address translation pair was registered in the address translation buffer 2, and the virtual address for the processing device to access the main memory was able to be translated into a real address.

The desired real address may be obtained by referencing the address translation buffer once again, or may be output from register 13 to signal line 11 via registers 8, 9, and 10.

That is, according to the present invention, it takes a lot of time to generate and maintain the
It is now possible to obtain a desired real address by referring to the address translation table in the main memory and register it in the address translation buffer without requiring any shadow processing that consumes resources.

In the above embodiment, both the first and second address conversion table 0) start addresses are stored in registers inside the processing device, but these may be stored as data in the main memory, for example. It's okay.

In that case, instead of outputting register 60.degree. 610 data, the necessary main memory access will be performed.

In the above embodiment, in order to simplify the explanation, address translation from a level 3 address to a level 2 address and address translation from a level 2 address to a level 1 address are each performed using one address translation table. The effectiveness of the present invention is clear even if this is due to a two-stage (generally multiple stages) chiffle, such as a segment chiffle and a page chiffle, as seen in many prior art techniques.

Furthermore, the present invention can be easily extended as follows.

That is, as mentioned earlier, the multiplicity of virtual addresses is not limited to the three levels shown in the embodiment, but may also be greater or lesser.

Generally, when there are (M+1) virtual addresses, there are M sets of address translation tables.

Therefore, in this case, the present invention can be implemented by providing M registers (or data areas on the main memory) indicating the start address of the address conversion table.

Furthermore, if the multiplicity of virtual addresses is made variable instead of being fixed on the hardware, the flexibility of the processing device can be increased and the performance improved.

The following methods can be considered for this purpose.

The second method is to notify the processing device of the virtual address multiplicity M in the form of data in the register 62 or main memory inside the processing device.

At this time, the processing device reads M, refers to M sets of address translation tables, and uses the result of referring to the 0th set of address translation tables as a real address.

However, in this method, if the first address of the address conversion table is stored as a register group inside the processing device, there is a restriction that M must be less than or equal to the total number of registers N.

The second method is to provide additional information for each register or data in which the start address of the address conversion table is written, and set therein information that specifies the order of address conversion.

In this case, the order itself is fixed by the register position or the data position on main memory, and only the first address conversion, the last address conversion, or both are made variable. There is also.

As described above, the present invention makes it possible to perform address translation without the need to create and maintain a shadow table in a virtual memory system where virtual addresses generally have a multiplexed structure. It was possible to eliminate the consumption of time and resources.

Regarding the present invention, one address translation time (total time required for translation from the highest virtual address to the real address)
This has the disadvantage that it becomes larger than when a shadow table is provided.

However, if the capacity of the address translation buffer is increased beyond a certain level, the probability of address translation occurring by referring to the address translation table can be sufficiently reduced, so the overhead for this will be a shadow of the overall program processing time. This is much smaller than the overhead associated with table creation and management, and processing capacity can be improved.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram of visiting a virtual storage system having dual address translation tables and shadow tables, and FIG. 2 is a block diagram showing an embodiment of the present invention. 2...Address translation buffer, 3...
Comparator, 4...Gate, 5...Table reference control circuit, 60 and 61...Register for holding the start address of the address conversion table, 7,
8 and 10...Selector, 9...Adder, 14...Main memory.

Claims (1)

[Claims] 1. In a virtual computer system realized in a computer system having virtual memory, there are M sets of address translation means, the first address translation means converts the virtual address of the virtual machine to a second address, and the first The address conversion means converts the first address into the (K+1)th address, and the M-th address conversion means converts the M-th address into a real address of the main storage device. =1.2,...M-1)
, an address translation buffer that holds an address translation pair indicating a virtual address of the virtual machine and a corresponding real address of the main storage device, and a processing device uses the address translation buffer to convert the virtual address of the virtual machine. When attempting to convert the address into the corresponding real address of the main memory, if the required address conversion pair does not exist in the address conversion buffer, by sequentially using the M stages of address conversion means. An address translation device characterized by obtaining a required real address and registering the real address together with a corresponding virtual address in the address translation buffer.