JPS59132483A - Address converting device - Google Patents

Abstract

PURPOSE:To eliminate the need for the presence of a shadow table and to improve the effectiveness of a program running time and a main storage area by making the hardware of a processor reference directly the 1st and the 2nd address converting table. CONSTITUTION:When a table reference control circuit 5 is started, it references at first the 1st address converting table. The head address of the 1st address converting table is stored in a register 60 and contents of the register 60 are inputted to an adder 9 via a selector 7. Then, the control circuit 5 reads the 2nd address converting table. The head address of the 2nd address converting table is stored in a register 61 and inputted to the adder 9 via the selector 7. A desired address converting pair is registered in an address converting buffer 2 through the operation above and the virtual address by which the processor accesses the main storage is converted into a real address.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a virtual computer system realized in a computer system having a virtual storage method,
In particular, the present invention relates to the address translation device.

A virtual memory method is a virtual address that is determined separately from the address (real address) that indicates the location of the data on the main memory when a processing device accesses data stored in the main memory. This refers to the method of access.

The virtual storage method has been adopted in many computer systems in recent years, and its details are well known, so further explanation will be omitted.

Note that the correspondence between virtual addresses and real addresses is generally defined by an address translation table managed by software. Also, the translation of a virtual address into a real address is called address translation.

A virtual computer is a process in which a real computer is used for time sharing, and hardware information (control registers, calculation registers, PSW, etc.) is set in the real hardware in each time slot. A real computer operates as if it were a separate computer in each time slot. Therefore, it is possible to run multiple different operating systems on one computer at an apparent time of F. and l・tesu.

The virtual computer method has recently been used in some computer systems.
Since this has already been implemented, a more detailed explanation is not necessary.

In the virtual computer method, 1. Virtual memory is generally implemented in a multi-level configuration. This is the basic background of the present invention, and will be explained below. Each virtual machine has a virtual address and a corresponding real address in order to access data on the main memory. However, the real address for the virtual machine cannot directly become the real address on the main storage device.

This is because the main storage must appear to each virtual machine as if it were exclusively owned. Therefore, the real address for each virtual computer is a virtual address for the real computer, and this is converted once again to become a real address on the main storage device.

As described above, the virtual memory system in the virtual machine system performs the following six stages of address conversion.

(1) Level 1: Real address on main storage (real address for the real computer) (2) Level 2: Virtual address for the real computer (real address for the virtual computer) (3) Level 3 = For the virtual computer Although the most basic three-level address has been shown in the virtual address of , it is clear that an arbitrary number of intermediate level addresses can be set between level 1 and level 3. Therefore, although the present invention can be applied to a general virtual storage system having multi-stage addresses as described later, a specific explanation will be given for the case of the six stages described above.

By the way, in a virtual memory system having three levels of addresses, the following two types of address translation tables are required. (1) First address conversion table Conversion from level address to level 2 address (2) Second address conversion table Conversion from level 2 address to level 1 address Generally (M-1-1) stage address In a virtual storage system having M types of address translation tables, M types of address translation tables are required.

However, conventionally, when actually accessing data in main memory using a virtual address, the hardware of the processing device cannot directly refer to the address conversion table.

This is because conventional processing device hardware uses the visited address obtained through one address conversion as the real address in a virtual computer system designed with an infinitely high degree of θ. For this reason, in a one-way computer/system, the software is responsible for preparing the shadow table described below in the main memory [~(,
It has been used as a reference for processing device hardware.

That is, first, first? From the contents of the address translation team, a correspondence table (shadow table) of level 1 addresses for all level 6 addresses is created, and this table is used to store data on the main memory separately from the first and second address translation tables. Store it as . When accessing the main memory in general, by referring to the shadow table instead of referring to the first and second address translation tables, the real address can be obtained through one 7-address translation.

FIG. 1 conceptually shows the relationship between address change tables of addresses at each level.

A computer system having a virtual memory method generally has an address translation function inside the processing unit. This is an associative memory device that stores multiple pairs of virtual addresses and corresponding real addresses.
tion Lookaside Buffer). Address translation buffers are a well-known technology and need no explanation.

When a virtual computer system is realized, the address conversion button 1 will store level 3 addresses and corresponding level 1 addresses. When accessing the main memory, if the desired address translation pair is not in the address translation buffer, the desired level 1 address is obtained by referring to the shadow table, and the level 1 address obtained is
Both the address and the original level 6 address are registered in the address translation buffer.

Above, an outline of the conventional technology that implements a virtual memory method in a virtual computer system has been described.

Next, problems in the prior art will be explained. The shadow table is convenient in that there is no need to be aware that the hardware of the processing unit is a virtual computer system, but this has some disadvantages in terms of performance.

The first point is that it takes a lot of time to generate a shadow table. In one virtual space, there may be several dozen or more pages, which are the minimum unit of address translation.

Referring to the first and second address translation tables for each of them and creating a shadow table will require an average of 10 program steps per page. Therefore, in order to generate one set of shadow tables, a program of up to several hundred thousand steps must be run.

The second point is that swapping pages in main memory
When it becomes necessary to update the information in the address translation table, not only the first or twentieth address translation table but also the shadow table must be updated. In reality, if it is difficult to partially update the shadow table, eK may invalidate the entire shadow table for that space. In this case, if the space is to be accessed again later, the shadow table must be regenerated, taking a long time as described above.

The sixth point is that the shadow table itself requires a very large storage capacity.

When several thousand pages exist in one space, a storage area of at least thousands of bytes is required as a shadow table. Since the shadow table must be resident in the main memory due to its nature, the shadow table occupies a considerable portion of the main memory.

As mentioned above, the shadow table realizes a virtual memory system in a virtual computer system using conventional processing unit hardware, but its creation and maintenance consumes a large amount of program execution time and main storage space. There are drawbacks to doing so.

Furthermore, although there is likely to be a large amount of data in a set of shadow tables that is never used, the program time and main storage area are equally consumed by these items. time and resources will be wasted.

An object of the present invention is to eliminate the need for a shadow table, which has the above-mentioned difficulties, by adding a new function to the hardware of a processing device, thereby increasing the program execution time and the effectiveness of the main storage area. It is something.

The gist of the present invention is that the hardware of the processing device
This makes it possible to directly refer to the address translation table of .

The content of the present invention will be explained below using an embodiment shown in FIG.

FIG. 2 is a block diagram showing part of a processing device in which the present invention is implemented.

In FIG. 2, the processing device is connected to the main memory 14 on the signal line 1.
is given a virtual address to access. Which one is input to the address conversion buffer 2 and converted into a real address. In detail, a virtual address is stored in the portion 20 of the address translation buffer 2, and a plurality of sets of corresponding real addresses are stored in the portion 21, and one set is selected by a portion of the virtual address of the signal 11M1. Output.

The virtual address output from part 20 of the address translation buffer is compared with virtual address 1 in comparator 6;
If they match, the corresponding real address is sent to the main memory as the desired address via the gate 4 and selector 10.
address line 11. If the results of the comparison in comparator B do not match, the table reference control circuit 5 is activated in order to refer to the address conversion table on the main memory and obtain the desired real address.

When the table reference control circuit 5 is activated, it first refers to the address conversion table of M1.

The register 60 stores the first address of the first address conversion table, and the contents of the register 60 are input to the adder 9 via the selector 7. Also, a part of the virtual address of the signal line 1 is input to the other side of the adder 9,
The result of this addition is applied to line 11 as a first address conversion table address, and reading from main memory 14 is performed.

The contents of the first address conversion table read from the main memory 14 are level 2 addresses. This is set in the read data register 13 via the read data line 12 from the main memory 14.

Next, the control circuit 5 reads the second address conversion table. The register 61 stores the first address of the second address conversion table, and is input to the adder 9 via the selector 7. A part of the level 2 address set in the register 16 is input to the other input of the adder 9, and the result of the addition is sent to the main memory access address line 11 via the selector 10 as a second address conversion table address. given to.

The desired real address is written in the second address conversion table read from the main memory 14. This is read via the main memory read data line 12 and set in the data register 13, from where it is written via the signal line 14 to the address translation buffer 20 portion 21.

At the same time, the virtual address given to the signal line 1 is also written into the address translation buffer 20 portion 20.

Through the above-described operations, the desired address translation pair was registered in the address translation buffer 2, and the processing device was able to convert the virtual address intended to access the main memory into a real address. The desired real address may be obtained by referring to the address translation buffer once again, or may be output from the register 16 to the signal line 11 via the registers 8, 9, and 10.

That is, according to the present invention, it takes a lot of time to generate and maintain the
It is now possible to obtain a desired real address by referring to the address translation table in the main memory and register it in the address translation buffer without any need for a shadow table that consumes resources.

In the above embodiment, it is assumed that the data is stored in the registers of the first and second address parts, but these may be stored as data in the main memory, for example. In that case, instead of outputting the data in registers 60 and 61, the necessary main memory access will be performed.

In the above embodiment, in order to simplify the explanation, address translation from a level 6 address to a level 2 address and address translation from a level 2 address to a level 1 address are each performed using one set of address translation tables. The effectiveness of the present invention is obvious even if this is due to a two-level (generally multiple-level) table such as a segment table and a page table as seen in many prior art techniques.

Furthermore, the present invention can be easily extended as follows. That is, as mentioned earlier, the multiplicity of virtual addresses is not limited to the six levels shown in the embodiment, but may be greater or lesser. Generally, when there are (M+1) virtual addresses, there are M sets of address translation tables. Therefore, in this case, the present invention can be implemented by providing M registers (or data areas on the main memory) indicating the start address of the address conversion table.

Furthermore, if the multiplicity of virtual addresses is made variable instead of being fixed on the hardware, the flexibility of the processing device can be increased and the performance improved.

The following methods can be considered for this purpose.

The second method is to notify the processing device of the virtual address multiplicity M in the form of data in the register 62 or main memory inside the processing device.

At this time, the processing device reads M, refers to M sets of address conversion tables, and uses the result of referencing the Mth group of address conversion tables as a real address. However, in this method, if the first address ' of the address conversion table is provided as a register group inside the processing device, there is a restriction that M must be less than or equal to the total number of registers N.

The second method is to provide additional information for each register or data in which the start address of the address conversion table is written, and to set information specifying the order of address conversion therein. In this case, the order itself is fixed depending on the register position or the data position on main memory, and only the first address translation, the last address translation, or both are variable. There is a way.

As described above, the present invention makes it possible to perform address translation without the need to create and maintain a shadow table in a virtual storage system in which virtual addresses generally have a multiple structure. A large amount of time and resource consumption associated with this process could be eliminated.

The present invention has the disadvantage that the time required for one address conversion (total time required for conversion from the highest address to the real address) is longer than when a shadow table is provided.

However, if the capacity of the address translation buffer is increased beyond a certain level, the probability of address translation occurring by referring to the address translation table can be sufficiently reduced, so the overhead for this will be a shadow of the overall program processing time. This is much smaller than the overhead associated with table creation and management, and processing capacity can be improved.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram illustrating a virtual storage system having dual address translation tables and shadow tables, and FIG. 2 is a block diagram showing an embodiment of the present invention. 2. Address conversion buffer 3... Comparator 4 Gate 5... Table reference control circuit 60 and 6 Registers 7, 8 and 10 that hold the start address of the address conversion table Selector 9 Adder 14 Main storage device Patent attorney Taku Takahashi/Main Diagram 2

Claims (1)

[Claims] In a virtual computer system realized in a computer system having virtual memory, there are M sets of address translation means, the first address translation means converts a virtual address of the virtual machine to a second address, and converts the virtual address of the virtual machine to a second address. The conversion means converts the first address into the (K+1)th address, and the M-th address conversion means converts the M-th address into a real address of the main storage device. 1.2.-M-1), an address translation buffer that holds an address translation pair indicating a virtual address of the virtual machine and a corresponding real address of the main storage device, and a current address translation multiplex of the processing device. and an indicator indicating a frequency M, and when a processing device attempts to convert a virtual address of a virtual machine to a corresponding real address of the main storage device using the address translation buffer, the required address translation pair is If it does not exist in the address translation buffer, the required real address is obtained by the address translation means of the number of stages indicated in the display among the M stages of address translation means, and the real address is converted to the corresponding virtual address. An address translation device characterized in that the address translation device registers the same with the address translation buffer.