JPH0816477A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To speed up matching processing for TLBs between respective EPUs in the multiprocessor system. CONSTITUTION:Copy TLBs 53a and 53b, and 63a and 63b of TLBs 11 and 21, and 31 and 41 in EPUs 1 and 2, and 3 and 4 are provided in SCUs 5a and 6a. When one of the EPUs 1, 2, 3, and 4 rewrites an address conversion table in a memory to erase ineffective address conversion pairs from the respective TLBs 1, 21, 31, and 41, the CTLBs 53a, 53b, 63a, and 63b are looked up with a logical address to be invalidated to detect the TLB wherein the address conversion pair to be invalidated is registered, and TLB invalidation processing is indicated to only the EPU having the TLB where the address conversion pair to be invalidated is registered to eliminate unnecessary TLB invalidation processing, thereby improving the performance of the system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and more particularly to synchronous control of an address translation buffer between multiprocessors.

[0002]

2. Description of the Related Art Recent computer systems employ a virtual memory system. In this case, an address conversion table is created to convert the logical address on the program into the actual address on the actual memory. This address conversion table is stored in the memory. For that purpose, an arithmetic processing unit (or processor, which decodes and executes instructions)
(Hereinafter referred to as EPU), each time the memory is accessed,
In order to convert a logical address to a real address, it is necessary to refer to the address conversion table on the memory. In order to reduce the overhead at this time, an address translation buffer (hereinafter referred to as TLB) that holds a plurality of translation pairs from a logical address to a real address is provided in the EPU by using the result of performing the address translation once. It is common to speed up address translation.

In recent years, a technique for constructing a tightly coupled multiprocessor system by using a plurality of such EPUs and improving the system performance has become extremely important. In this case, one of the technical problems that must be overcome is the problem of guaranteeing the consistency of TLB contents between a plurality of EPUs. For example, a page required by a certain EPU (a unit of data size when the address space is divided into units of a certain size; address conversion is executed in this page unit) is not present in the memory. When detected,
This EPU notifies the OS of a page fault. The OS selects an unnecessary page from the memory, and the above-mentioned EP existing on the unnecessary page and an external storage device such as a disk.
The replacement process with the page required by U is performed.

At this time, the page newly allocated in the memory is allocated the previous real address of the page flushed to the external storage device, and the EPU associates the logical address of the new page with the real address. The contents of the address translation table are rewritten so that At this time, if there is a TLB that has registered an address translation pair corresponding to the old page that has been flushed to the external storage device, this old address translation pair is invalidated, and synchronization control is required to match the contents of all TLBs. become.

Specifically, the above EPU sends the logical address of the page to be invalidated to the TLB in its own EPU and the TLB in another EPU, searches all TLBs by this logical address, and invalidates. When an address translation pair to be converted is detected, this address translation pair is erased.
This invalidation processing of the address translation pair is executed as a TLB synchronization clear instruction.

Referring to FIG. 4, which is a block diagram showing the main part of the TLB synchronization invalidation processing in the conventional multiprocessor, this multiprocessor system has four Es.
It has PUs 1, 2, 3 and 4 and two system control units (hereinafter referred to as SCU) 5b and 6b. The memory etc. which are not necessary for explanation are omitted.

Within each EPU 1, 2, 3 and 4,
TLBs 11, 21, 31 and 41 are provided respectively. EPU1 and 2 are SCU5 via bus 70
b, and EPUs 3 and 4 connect to S via bus 71.
It is connected to the CU 6b. SCU5b and SCU6b
Are connected to each other via a bus 72,
And 72 are composed of control lines, address lines and data lines.

Further, the SCU 5b includes a selector 51, a register 52, drive buffers 56 to 59 and a control circuit 55.
The bus 70 is connected to the drive buffer 57, and the output end of the drive buffer 57 is connected to one input end of the selector 51 and the control circuit 55. Selector 51
Is connected to register 52, its outputs are connected to drive buffers 56 and 58, respectively, and its outputs are connected to data buses 70 and 72, respectively.

On the other hand, the input end of the drive buffer 59 is connected to the data bus 72, and the output end thereof is connected to the other input ends of the selector 51 and the control circuit 55, respectively. One output end of the control circuit 55 is the other input end of the drive buffer 56, and the other output end of the control circuit 55 is the drive buffer 58.
Are connected to the other input ends of the.

The SCU 6b has the same configuration as the SCU 5b, and the reference numerals 51 and 61, 52 and 62, 53 and 6 of the constituent elements.
3, 54 and 64, 56 and 66, 57 and 67 and 58 and 68, respectively.

A case where the EPU 2 executes the TLB synchronization clear command will be described. The TLB synchronous clear instruction specifies the logical address of the TLB to be invalidated. When EPU2 decodes the TLB sync clear command, the specified TLB
The address translation pair to be invalidated is erased from the TLB 21 according to the invalidation logical address. At the same time, EPU2 is T
The LB invalidation request and the TLB invalidation logical address are sent to the bus 70.
It is sent to the SCU 5b using the control line and the address line. The TLB invalidation request is notified to the control circuit 55 via the drive buffer 57, and the TLB invalidation logical address is set in the register 52 through the selector 51.

The control circuit 55 sends the TLB invalidation request and the TLB invalidation logical address to the SCU 6b by using the control line and the address line of the bus 72. The TLB invalidation request is notified to the control circuit 65, and the TLB invalidation logical address is set in the register 62 through the selector 61.

Next, the control circuits 55 and 65 use the control lines and address lines of the bus 70 and the bus 71 to make the TLB.
The invalidation request and TLB invalidation logical address are set to EPU1, 3
And send to 4. E who received the TLB invalidation request
The PUs 1, 3 and 4 erase the address translation pair to be invalidated from the respective TLBs 11, 31 and 41 according to the TLB invalidation logical address.

By this series of processing, each EPU 1, 2,
The conversion pairs to be invalidated are deleted from TLBs 11, 21, 31 and 41 in 3 and 4, and TLBs 11, 21,
The contents of 31 and 41 are matched. When this invalidation processing ends, EPU 1 uses the control line of bus 70 to notify SCU 5b that the TLB invalidation processing has ended, and EPUs 3 and 4 use the control line of bus 71 to disable TLB. The SCU 6b is notified that the conversion processing has been completed.

The end signal of the TLB invalidation process notified to the SCU 6b is notified to the SCU 5b through the dedicated wiring 74. The SCU 5b notifies the EPU 2 of the end signal of each TLB invalidation processing through the control line of the bus 70. E
When PU2 receives all the end signals of the TLB invalidation processing from EPUs 1, 3 and 4, it judges that this TLB synchronization clear instruction has ended and starts the processing of a new instruction.

When the EPU 3 or 4 executes the TLB synchronization clear command, the same procedure is executed.
The termination signal of the LB invalidation process is sent to the SC through the dedicated wiring 74.
Notify U5b.

Another example of conventional address translation control is disclosed in Japanese Patent Laid-Open No. 4-352047. The address translation control described in the publication is such that, when a microprocessor rewrites the contents corresponding to the logical page of the address translation table, at the same time as invalidating its own address translation buffer with an address translation invalidating instruction, all other microprocessors The address translation buffer in the processor can be invalidated. Therefore, the logical address specified by the invalidation instruction is output to the outside of the microprocessor chip, the logical address is input to another microprocessor, and the translation pair corresponding to the logical address is erased from the address translation buffer. It is a thing.

[0018]

In the conventional multiprocessor system described above, when a certain EPU rewrites the address conversion table in the memory and executes the TLB synchronous clear instruction, the TLB invalidation logical address is given to all EPUs. It had to be sent out and the TLB invalidation process had to be executed equally in all EPUs. Further, the EPU which executes the TLB synchronization clear instruction can only start executing a new instruction after confirming the completion of the TLB invalidation processing of all the other EPUs.

On the other hand, in reality, each EPU is often assigned a unique address space, and the number of TLBs that actually hold an address translation pair that should be rendered ineffective by the TLB synchronization clear instruction is equal to the number of TLBs. Very few. Also multiple E
The address space shared by the PU is often controlled so as to be resident in the memory, and the TLB invalidation process itself by the TLB synchronous clear instruction is very small.

However, in the conventional multiprocessor system, every time an TLB synchronous clear instruction is executed, all EPUs including most EPUs that do not actually need to invalidate the TLB address translation pair. There is a problem in that the performance of the overhead is lowered due to the invalidation processing of the address translation pair of the TLB. Moreover, TLB
The EPU executing the synchronous clear command is
You have to wait for the end of the TLB invalidation process from the PU,
For example, even with one EPU, there is a problem in that if the TLB invalidation processing is suspended because an instruction having a very long execution time is being executed, the performance is significantly deteriorated.

By the way, the execution of the TLB synchronous clear instruction is a problem that necessarily occurs when one address space is allocated to one EPU, and the TLB synchronous clear instruction appears in proportion to the increase in the number of EPUs. The number also increases proportionally. Therefore, in the conventional multiprocessor system, when the number of EPUs is increased to improve the system performance, the problem that the system performance is deteriorated due to the overhead of the TLB synchronization clear instruction described above becomes extremely serious. Was there.

The object of the present invention is made in view of the above-mentioned problems, and each EPU of a multiprocessor system is provided.
It is to realize the speedup of the TLB matching process between the two.

[0023]

A feature of a multiprocessor system of the present invention is that an arithmetic processing unit has an address translation buffer including a plurality of address translation pairs of a logical address and a real address. Individual preparation,
In a multiprocessor system which executes an address translation buffer sync clear instruction to erase this address translation pair when the address translation pair to be ineffective is detected, a copy of each content of the address translation buffer is transferred. When a plurality of storage means to be stored and a predetermined arithmetic processing unit among the plurality of arithmetic processing units execute the address translation buffer synchronization clear instruction to execute a plurality of address translation buffer invalidation processes , Means for searching the contents of the plurality of storage means with the invalidation logical address of the address translation buffer, and the invalidation logical address of the address translation buffer in any one of the plurality of storage means according to the search result. A means to detect whether it is registered, and the invalidation logical address according to the detection result. To the plurality of processing units corresponding to the recorded has been the storage means, in that a first sending means for sending the address translation buffer invalidation request by the invalidation logical address.

Further, the plurality of storage means may be configured to hold only the logical address parts of the corresponding address translation buffers.

Further, there is a system control unit connected to the plurality of arithmetic processing units, and the system control unit is provided with a plurality of storage means corresponding to the address conversion buffers respectively included in the plurality of arithmetic processing units. May be.

Furthermore, among the plurality of processing units, each of the plurality of system control units connected to a plurality of predetermined processing units has the plurality of storage means and is connected to the plurality of storage units. A storage unit for holding the invalidation logical address sent by the arithmetic processing unit when any one of a plurality of arithmetic processing units executes the address translation synchronization clear instruction to execute the invalidation processing of the address translation buffer; One holding means, a means for searching the contents of the plurality of storage means based on the held invalidation logical address, and an arithmetic processing device corresponding to each of the plurality of storage means according to the search result. The address translation buffer invalidating request to the other first system control device and the address translation buffer to another system control device. Second sending means for sending the invalidation request, second holding means for holding the invalidation logical address sent from another system control device, and a plurality of the plurality of invalidating logical addresses based on the held invalidation logical address. And a third sending means for sending the address translation buffer invalidation request sent from the other system control device to the arithmetic processing device according to the search result. it can.

Further, the address translation generated by each of the plurality of system control devices to which the plurality of predetermined arithmetic processing devices are connected is generated from the arithmetic processing device and the other system control device. In response to the buffer invalidation request, the address holding buffer invalidating request is sent to the first holding unit that holds the invalidating logical address, the unit that searches the contents of the plurality of storage units, and the plurality of arithmetic processing units. The first sending means for sending may be configured to be shared when registering a new address translation pair and when indexing the invalidated logical address.

Further, as a result of each of the plurality of system control devices to which the plurality of predetermined arithmetic processing units are connected searching for the plurality of storage means by the invalidation logical address of the address translation buffer,
It is detected that the invalidation logical address is not registered, and an address translation buffer invalidation request by the invalidation logical address is sent to the arithmetic processing unit having the address translation buffer corresponding to the storage means. Means may be provided for notifying and notifying the predetermined arithmetic processing unit executing the address translation buffer synchronization clear instruction that the address translation buffer invalidation processing for the arithmetic processing unit has been completed.

Furthermore, each of the plurality of system control devices to which the predetermined plurality of arithmetic processing devices are connected uses the invalidation logical address of the address translation buffer received from another system control device. As a result of searching the plurality of storage means, when it is detected that the invalidation logical address is not registered, the end of the invalidation processing of the address translation buffer corresponding to the plurality of storage means is terminated by the other system control. And a means for notifying the device, and when the end of the invalidation process is received from another system control device, the end notification is sent to the predetermined arithmetic processing device executing the address translation buffer synchronization clear instruction. Means for doing so can also be provided.

[0030]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a multiprocessor system according to an embodiment of the present invention. In FIG. 1, the same components as those of FIG. 4 showing a conventional multiprocessor system are designated by the same reference numerals. The multiprocessor system of this embodiment has four EPUs 1, 2, 3 and 4
And 4EP consisting of two SCUs 5a and 6a
A U-multiprocessor system, which does not directly relate to the present invention, is omitted.

Referring again to FIG. 1, EPUs 1 and 2
Is connected to the SCU 5a via the bus 70, and the EPUs 3 and 4 are connected to the SCU 6a via the bus 71. The SCU 5a and the SCU 6a are connected to each other via a bus 72, and special control between them is performed by dedicated wirings 73 and 74.

Both 71 and 72 are composed of control lines, address lines and data lines. EPU1,
2, 3 and 4 have TLBs 11, 21, 31 and 41 respectively. Each of the TLBs 11, 21, 31, and 41 is composed of a Key part and a Data part. The Key part stores the logical address used for memory access, and the Data part stores the logical address registered in the Key part. The real address obtained by executing the address conversion is registered in the position corresponding to the logical address of the Key part.

Each TLB 11, 21, 31 and 41
Holds a plurality of such address translation pairs. T
The structure of the LB is generally known and
It may have an associative structure or a set associative structure.

When the TLB has a full associative structure, all the bits of the logical address except for the in-page address which is not necessary for the address conversion are registered in the Key section. Further, the address translation pair can be registered in any place of all the entries of the TLB.

On the other hand, referring to FIG. 2 showing a general example of the set associative structure of the TLB, a logical address part having a key address part 206 of the upper bit and an addressing part 207 of the lower bit and its corresponding part. A logical address 201 consisting of an in-page address 208 of a page, a register 209 for temporarily storing the key address portion 206 used in memory access, and a real address obtained by address-converting the logical address stored at this address are registered in the register. A write address register 202 including a register 210 stored at a position corresponding to a logical address in 209, and a register 2 corresponding to an address designated by the address designation unit 207 of the logical address 201.
09 is stored in the key address 211 and the real address data of the register 210 is stored in the real address part 212, and the comparator 204 for comparing the contents of the key address 211 with the contents of the key address part 206. And the real address 205 corresponding to the logical address 201 has TLB20 in the upper bits.
The real address part 21 in which the real address part 212 of 3 is registered
3 and an in-page address 214 in which the in-page address 208 of the logical address 201 is registered.

That is, the registration location of the address translation pair is
It is designated by a plurality of fixed bits of the address designation unit 207 excluding the in-page address 208 and the key address unit 206 from the logical address 201 designated on the program. The address designating unit 207 is prepared with a bit number capable of designating the number of registered addresses of the TLB 203.

In the key address 211 of the TLB 203, the key address part 2 obtained by removing the in-page address 208 and the address designating part 207 from the logical address 201
06 is registered. In addition, the address designation unit 207 generally uses the logical address 20 excluding the in-page address 208.
The lower part of the address within 1 is used. The registration of the address translation pair is controlled by a control circuit (not shown), and the control timing is triggered by the comparison result of the comparator 204. In the present embodiment, description will be made assuming that the TLB having the set associative structure is adopted.

Next, the internal structure of the SCUs 5a and 6a will be described. The selector 51 selects one of the data sent through the bus 70 and the bus 72,
Set in register 52. The selector 61 is the bus 71
And one of the data sent through the bus 72 is selected and set in the register 62. The data set in the registers 52 and 62 is the address data sent through the address lines of the buses 70, 71 and 72. The data sent through the address lines of the buses 70, 71, and 72 are data used in memory stores and the like and are not directly related to the present invention.
It will be omitted in the following description.

The lower part of the address data set in the registers 52 and 62 is a copy TLB (hereinafter CT).
(Referred to as LB) 53a, 53b, 63a and 63b, and used as the addressing section of each CTLB. The upper part of the remaining address data is CTL.
It is supplied to comparators 54a, 54b, 64a and 64b for comparison with the contents of the key part of B53a, 53b, 63a and 63b.

CTLB 53a, 53b, 63a and 6
3b is a memory for holding a copy of the contents of the TLBs 11, 21, 31, and 41, respectively. CTLB53a,
53b, 63a and 63b are TLB11, 21, 31
Of the contents of 41 and 41, only the contents of the Key part are held, and the amount of hardware is reduced. CTLB 53a, 53b, 63a and 63b
Update the contents of TLB 11, 21, 31 or 41
This is done at the same time when the address translation pair of is updated.

That is, when converting a new logical address into a real address in EPU 1, 2, 3 or 4, the address conversion pair to be calculated is TLB 11, 21, 31 or 41.
When the new address translation pair is registered in the TLB 11, 21, 31 or 41, the CTLB 53a, 5
The contents of 3b, 63a and 63b are also updated.

Here, the case where the address translation is executed in the EPU 3 and a new address translation pair is registered in the TLB 31 will be described. At this time, at the same time, the logical address part of the newly registered address translation pair, the TLB update instruction, and the EPU number indicating EPU3 are sent to the SCU 6a through the address line and control line of the bus 71.

The logical address sent to the SCU 6a is set in the register 62 through the selector 61, and the TL
The B update instruction and the EPU number are notified to the control circuit 65.

Then, according to an instruction from the control circuit 65, CTLB6 of the logical addresses set in the register 62 is
CT by the addressing unit that specifies the address of 3a
The address position of the LB 63a to be updated is designated. By this designation, the contents of the higher-order address part of the logical address set in the register 62 excluding the address designating part, that is, the Key part of the TLB 31 is CTLB 63a.
Is registered at a predetermined position of. By this series of processing,
Key of address translation pair newly registered in TLB31
A copy of the copy has been copied to the CTLB 63a.
The update processing of the other CTLBs 53a, 53b and 63b is also performed in the same manner.

CTLB 53a, 53b, 63a and 6
The index of 3b is CTLB5 by the addressing part of the logical addresses set in the registers 52 and 62.
3a, 53b, 63a and 63b are addressed, and the contents of the CTLBs 53a, 53b, 63a and 63b are read from the address position.

The CTLBs 53a and 53 thus read out
The contents of b, 63a and 63b are the contents of the comparator 54, respectively.
a, 54b, 64a and 64b. The comparators 54a, 54b, 64a and 64b are connected to the register 52.
And the upper address part of the logical address set in the logical addresses 62 and 62 excluding the lower address specification part and the CTLB 53
Comparators for respectively comparing the contents read from a, 53b, 63a and 63b, and the comparison results are notified to the control circuits 55 and 65, respectively. Control circuit 55
Reference numerals 65 and 65 are control circuits that perform various controls according to input information.

Next, the operation of the TLB synchronization clear instruction, which is a feature of the present invention, will be described with reference to FIG. 1 and FIG. 3 showing a flowchart for explaining the operation. EPU2
Will execute a TLB synchronization clear instruction. E
When PU2 decodes the TLB sync clear instruction, the TLB invalidate logical address specified by the instruction is fetched. According to this TLB invalidation logical address, EPU2
Deletes the address translation pair to be invalidated from the TLB 21. At the same time, the EPU 2 sends the TLB invalidation request and the TLB invalidation logical address to the SCU 5a using the control line and the address line of the bus 70 (Fig. 3-301). At this time, the EPU number indicating EPU2 is also sent to the SCU 5a through the control line of the bus 70. The TLB invalidation request and the EPU number are sent to the control circuit 5 via the drive buffer 57.
5 is notified, and the TLB invalidation logical address is the selector 5
1 to the register 52 (see FIG. 3-30).
2).

The control circuit 55 uses the control line and address line of the bus 72 via the drive buffer 58 to drive the TLB.
The invalidation request and the TLB invalidation logical address are sent to the SCU 6a (FIG. 3-303). The TLB invalidation request is notified to the control circuit 65 by the dedicated wiring 73, and the TLB invalidation logical address is set in the register 62 through the selector 61 (FIG. 3-304).

Next, the CTLB 53a, 53b, 63a and 63b are indexed by the addressing portion of the TLB invalidating logical address set in the registers 52 and 62 (FIG. 3-305), and the CTLB 53a, 53b, 63a.
And the contents of 63b are read out, and the comparator 5
4a, 54b, 64a and 64b.

Comparators 54a, 54b, 64a and 64
In b, CTLB 53a, 53b, 63a and 63b
The contents read from the above are compared with the higher-order address part of the TLB invalidation logical addresses set in the registers 52 and 62, excluding the addressing part (FIG. 3-3).
06), the comparison result is notified to the control circuits 55 and 65. If the result of the comparison shows a match,
If the corresponding TLBs 11, 21, 31, and 41 indicate that there is an address translation pair to be invalidated, and if there is a mismatch, then there is no address translation pair to be invalidated in the corresponding TLB 11, 21, 31, and 41. It is shown that.

To make the description concrete, the comparator 54
A match is detected at a, 54b and 64b and the comparator 64
It is assumed that a mismatch is detected in a. The control circuits 55 and 65 erase the copy of the Key part to be invalidated from the CTLBs 53a, 53b and 63b in which the match is detected (FIG. 3-307). At the same time, the control and address lines of buses 70 and 71 are used to detect the CTLB for which a match has been detected.
EPU1 corresponding to 53a and 53b of 53a, 53b and 63b excluding 53b executing the clear instruction
And 4 to TLB invalidation request and registers 52 and 62
The TLB invalidation logical address held in is transmitted (FIG. 3-308). At this time, the CTLB6 in which a mismatch is detected with the EPU2 executing the TLB synchronization clear command
The transmission of the TLB invalidation request is suppressed to the EPU 3 corresponding to 3a. Upon receiving the TLB invalidation request and the TLB invalidation logical address, the EPUs 1 and 4 erase the address translation pair to be invalidated from the TLBs 11 and 41 in accordance with the transmitted TLB invalidation logical address.
The control lines of the buses 70 and 71 are used to notify the SCUs 5a and 6a that the B invalidation processing is completed. The SCU 6a notifies the SCU 5a of the end notification of the SCU 6a using the dedicated wiring 74.

The end notification of both TLB invalidation processing is sent to the control circuit 65 (FIG. 3-309). The control circuit 5 which has received the mismatched comparison result from the comparator 64a.
5 recognizes that there is no address translation pair to be invalidated in the corresponding TLB 31, and T for EPU3
It is determined that the LB invalidation process is not necessary, and the dedicated wiring 74 is used to notify that the TLB invalidation process of the EPU 3 is completed.
Notify the CU 5a. The end notification of this TLB invalidation processing is also notified to the control circuit 55 (FIG. 3-311).

In the control circuit 55, all E except EPU2
When the notification of the end of the TLB invalidation processing is reported from the PUs 1, 3 and 4, the representative signal of the end of the TLB invalidation processing is notified to the EPU2 using the control line of the bus 70 (FIG. 3-3).
12). Upon receiving the representative signal indicating the end of the TLB invalidation processing, the EPU 2 determines that the TLB synchronization clear instruction has ended, and starts processing a new instruction. The same is done when EPUs 1, 3 and 4 execute the TLB sync clear instruction.

In the multiprocessor system of the present invention, when increasing the number of EPUs, there are two methods: increasing the number of EPUs connected to each SCU and increasing the number of SCUs in the system. 1 SCU
When the number of EPUs connected to the SCU is increased, the CTLB in the SCU is added accordingly. The present invention
Since the mechanism for accelerating the TLB invalidation process is constructed in the SCU, the EPU can be executed by any of the above methods.
Even when the number of units is increased, the present invention can be realized without increasing the hardware amount of EPU. Therefore, the conventional EPU can be used as it is.

[0055]

As described above, the multiprocessor system of the present invention is provided with a copy TLB (CTLB) for storing a copy of the contents of the TLB in the SCU, and indexes this CTLB when executing the TLB synchronization clear instruction. Therefore, it is determined whether the TLB invalidation process is actually necessary, and the TLB invalidation process is immediately terminated for the PEU that does not need the TLB invalidation process, thereby unnecessary overhead of the TLB invalidation process. Can be reduced,
This has the effect of significantly improving the performance of the entire system.

Further, since a mechanism for speeding up the TLB invalidation processing is built in the SCU, it is not necessary to increase the hardware of the EPU even when the number of EPUs is increased, and the speed of the TLB matching processing between the EPUs is high. This has the effect of achieving high efficiency and easily expanding the system.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a multiprocessor according to the present invention.

FIG. 2 is a block diagram showing a general example of a set associative configuration applied to one embodiment of the present invention.

FIG. 3 is a flowchart illustrating an embodiment of the present invention.

FIG. 4 is a block diagram showing an example of a conventional multiprocessor system.

[Explanation of symbols]

 1 to 4 EPU 5a, 6a SCU 11, 21, 31, 41 TLB 51, 61 selector 52, 62 register 53a, 53b, 63a, 63b CTLB 54a, 54b, 64a, 64b comparator 55, 65 control circuit 56-59, 66-69 drive buffer 70-72 bus line 73, 74 dedicated wiring

Claims (7)

[Claims] 1. An arithmetic processing unit has an address translation buffer containing a plurality of address translation pairs of a logical address and a real address, and the arithmetic processing unit is provided with a plurality of address translation pairs to detect ineffective address translation pairs. In the multiprocessor system for executing the address translation buffer synchronous clear command to erase the address translation pair, a plurality of storage means for transferring and storing a copy of each content of the address translation buffer; When a predetermined arithmetic processing unit among the arithmetic processing units of 1) executes the address translation buffer synchronization clear instruction to execute the invalidation processing of the plurality of address translation buffers, the invalidation logical address of the address translation buffer is used. A means for searching the contents of the plurality of storage means, and a means for searching the plurality of storage means according to the search result. A means for detecting whether the invalidation logical address of the address translation buffer is registered in any one of them, and the plurality of arithmetic processes corresponding to the storage means in which the invalidation logical address is registered according to the detection result. A multiprocessor system comprising: a first sending unit for sending an address translation buffer invalidation request by the invalidation logical address to the device. 2. The multiprocessor system according to claim 1, wherein each of the plurality of storage units is configured to hold only a logical address portion of the corresponding address translation buffer. 3. A system control device connected to the plurality of arithmetic processing devices, the system control device comprising a plurality of storage means corresponding to the address translation buffers respectively included in the plurality of arithmetic processing devices. The multiprocessor system according to claim 1, wherein: 4. The plurality of system control devices, each of which is connected to a plurality of predetermined arithmetic processing devices among the plurality of arithmetic processing devices, has the plurality of storage means and is connected to the plurality of system control devices. A first holding unit holds the invalidation logical address transmitted by the arithmetic processing unit when any one of the arithmetic processing units executes the address translation synchronization clear instruction to execute the invalidation processing of the address translation buffer. Holding means, means for searching the contents of the plurality of storage means based on the held invalidation logical addresses, and the arithmetic processing device corresponding to the plurality of storage means according to the search result. The first transmission means for transmitting the address translation buffer invalidation request, and the address translation buffer invalidation request to the other system control device. And second storage means for storing the invalidation logical address transmitted from another system control device, and the plurality of storage means by the stored invalidation logical address. And a third sending means for sending the address translation buffer invalidation request sent from the other system control device to the arithmetic processing device according to the search result. The multiprocessor system according to claim 1. 5. The address translation generated by each of the plurality of system control devices to which the plurality of predetermined arithmetic processing devices are connected is generated from the arithmetic processing device and the other system control device, respectively. In response to the buffer invalidation request, the address holding buffer invalidating request is sent to the first holding unit that holds the invalidating logical address, the unit that searches the contents of the plurality of storage units, and the plurality of arithmetic processing units. 2. The multiprocessor system according to claim 1, wherein the first sending means for sending is configured to be shared during registration of the new address translation pair and indexing of the invalidated logical address. . 6. The result of each of the plurality of system control devices to which the plurality of predetermined processing units are connected searching for the plurality of storage means by the invalidation logical address of the address translation buffer, Detecting that the invalidation logical address is not registered, and suppressing sending of the address translation buffer invalidation request by the invalidation logical address to the arithmetic processing unit having the address translation buffer corresponding to the storage means. And further comprising means for notifying the predetermined arithmetic processing unit executing the address translation buffer synchronization clear instruction that the address translation buffer invalidation processing for the arithmetic processing unit has been completed. Item 1
The described multiprocessor system. 7. Each of the plurality of system control devices to which the plurality of predetermined arithmetic processing devices are connected uses the invalidation logical address of the address translation buffer received from another system control device. When it is detected that the invalidation logical address is not registered as a result of searching the storage means, the end of the invalidation processing of the address translation buffer corresponding to the plurality of storage means is terminated by the other system control device. And an end notification of the invalidation process from another system control device, the end notification is sent to the predetermined arithmetic processing device executing the address translation buffer synchronization clear instruction. The multiprocessor system according to claim 1, further comprising means.