JPH05298185A - Virtual storage system and device - Google Patents

Abstract

PURPOSE:To prevent the delay of a processing by the address conversion processing of the next page. CONSTITUTION:Whether the next page of the page when the present instruction exists in A TLB 9 or not is investigated in parallel with the execution of an instruction. When it does not exist, a logical page/address showing the next page is delivered to an address conversion processing part 7. The address conversion processing part 7 converts the logical page/address of the next page to a physical page/address by using an address conversion table. The physical address and the corresponding logical address obtained by the address conversion processing part 7 are written in a TLB register 10 and at the same time, an effective bit V is set to 1. When the processing reaches the next page, the logical address is converted into the physical address by referring to the content of the TLB register 10 and the logical-physical address pair of the TLB register 10 is registered in a TLB 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer adopting a virtual memory system, and more particularly to a virtual memory system and apparatus characterized by preliminarily performing an address conversion process for a page next to a currently accessed page. It is a thing.

[0002]

2. Description of the Related Art Most of recent computers employ a virtual memory system in which a user can develop a program by using a virtual address space much larger than a main memory of the computer. The virtual address space at this time is called a logical address space, which is realized by a secondary storage device such as a disk device, and the main memory owned by the computer is called a physical address space.

The logical address space is divided into areas called sections of a fixed size, and one section is divided into units called pages of a fixed size. In order for the CPU to execute an instruction, it is necessary that the instruction exists in the main memory. Therefore, the page in the logical address space in which the instruction that the CPU is going to execute exists must be loaded in the main memory. .. At this time, it must be previously determined to which page in the physical address space each page in the logical address space corresponds. This correspondence is determined by the address conversion table stored in the main memory. The address translation table consists of a section table and a page table.

FIG. 3 is a diagram showing a process of converting a logical address to a physical address by the two-stage paging method. As shown in the figure, the section index (Sx) of the logical address specifies the offset from the beginning of the section table, and the section table entry is determined. The page table base (PTB) of the section table entry indicates the beginning of the page table, and the page table entry is obtained by the page index (Px). The page table entry holds a page frame number (PFN), which is a page in the physical space. Therefore, page ij in the logical space is assigned to page j.

The above dynamic address conversion (Dynamic Address
Translation: DAT) is used to translate a logical address to a physical address. However, since it takes time to look up the address translation table, in reality, some logical addresses and physical addresses are paired with a TLB (Translation Lookasi).
In many cases, de buffer) is provided in the chip to speed up the process. Therefore, when the CPU accesses a new page, it first searches the TLB and hits the TL.
The physical memory obtained in B is used to access the main memory, and when there is a mishit, the physical address is obtained by DAT. If the page containing the instruction to be executed is not in the main memory, the secondary storage device is accessed by exception processing and the required page is loaded into the designated page in the main memory.

[0006]

When the end of the page is reached, the TLB of the next page is searched for only when the end of the page is reached. At this time, if the TLB is hit, the address conversion is performed immediately. There is almost no delay in processing. However, it is unlikely that the TLB will be hit when the processing moves to a new page under the condition that the instructions arranged in succession are processed, and the DAT processing needs to be performed. When the DAT processing is executed, since the address conversion table is referred to,
The processing is slowed because the main memory is accessed and the update bit and the reference bit are set. Moreover, the arithmetic unit used for address translation is common to the arithmetic unit used for instruction processing. Sometimes pipeline processing had to be stopped, causing significant delays. The present invention was created in view of this point, and when the instructions are continuously executed, the next page search or DAT is performed in parallel with the currently executing instruction, and the address of the new page is obtained. The purpose is to prevent processing delay due to conversion processing.

[0007]

Therefore, according to the virtual storage system of claim 1 of the present invention, an address translation table for performing translation between a logical address and a physical address and a TLB for holding a part thereof are provided. A virtual memory system in a computer of the virtual memory system that has, when a central processing unit is executing an instruction, a TLB search is performed in advance for a page next to the page in which the instruction exists, and a TLB is missed. Is characterized in that the dynamic address translation is immediately performed in parallel with the currently executed instruction processing. A virtual storage device according to claim 2 of the present invention is a virtual storage device in a virtual storage system computer having an address translation table for performing translation between a logical address and a physical address and a TLB for holding a part thereof. , A program counter (1) in which a logical address consisting of a page address part and an offset part is set, an address conversion processing part (7) having an address conversion table (5) and an address conversion arithmetic unit (6), A TLB register (10) having a logical page address part, a physical page address part and a valid bit, and a TLB (9) having a plurality of entries in which a pair of a logical page address and a physical page address is written, The control unit includes a +1 circuit (2), a comparator (3), and a control unit (4) for controlling each unit of the device.
(4) is for setting the logical page address of the next page by inputting the logical page address of the program counter (1) to the +1 circuit (2) when the offset value of the program counter (1) reaches a predetermined value. The address is obtained, the logical page address of the next page is obtained from the entry corresponding to the next page of TLB (9), the logical page address of the next page obtained from the +1 circuit (2), and the logical page address obtained from the TLB (9) are obtained. The logical page address of the page is compared with the comparator (3), and if the comparison result shows a mismatch, the logical page address of the next page obtained from the +1 circuit (2) is sent to the address conversion processing unit (7). Sending address conversion processing is executed, and address conversion processing unit
The physical page address and the corresponding logical page address output from (7) are written to the TLB register (10), and the valid bit of the TLB register (10) is set to a value indicating that the program counter (1) has the following value. When the value immediately before moving to the page is shown, the valid bit of the TLB register (10) is checked, and if the valid bit shows valid, the physical page address of the TLB register (10) is used to read the next page. Prefetch the first instruction, and also TLB register
It is characterized by being configured to perform control for registering the pair of the logical page address and the physical page address of (10) in the TLB (9). A virtual memory device according to a third aspect of the present invention is the virtual memory device according to the second aspect, wherein the address translation arithmetic device (6) is an arithmetic device different from the arithmetic device for performing instruction processing. To do.

[0008]

The operation of the virtual memory system according to claim 1 will be described. In the virtual memory system according to the first aspect, during execution of an instruction of the central processing unit, it is checked whether or not the page next to the page in which the instruction exists is present in the TLB. If it does not exist, DAT is performed to find the physical page address where the next page exists. This DAT processing is performed in parallel with the instruction processing. The physical page address obtained by DAT and the corresponding logical page address are stored in suitable storage means.

The operation of the virtual storage device according to the second aspect will be described. When the offset value of the program counter (1) reaches a predetermined value, the page value of the program counter (1) is incremented by 1, and the logical page address of the next page is calculated. Check whether it is registered in TLB (9). If it is not registered, the logical page address of the next page is sent to the address translation processing unit (7) to execute DAT. The physical page address and the corresponding logical page address obtained by the address conversion processing unit (7) are written in the TLB register (10). At this time, the valid bit of the TLB register (10) is set to 1 (indicating validity).

When the program counter (1) indicates a value immediately before the next page is transferred (a state in which a few more instructions remain by the end of the page) and the effective bit of the TLB register (10) is 1, The physical page address of the TLB register (10) is used to prefetch the first instruction of the next page, and the pair of the logical page address and physical page address of the TLB register (10) is registered in the TLB (9). It should be noted that this prefetch is naturally performed on condition that the instruction buffer has a free space.

The operation of the virtual storage device according to the third aspect will be described. In the virtual storage device according to claim 3, the address translation processing unit (6) in the address translation processing unit (7) is a computing unit different from the computing unit used in the instruction processing, and therefore the address translation processing unit It is not necessary to stop instruction processing while (7) is performing DAT processing.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram for explaining an address conversion process in the next page DAT processing of the present invention. In the figure, 7 is an address conversion processing unit, 9 is a TLB, and 10 is a TLB register. The address translation processing unit 7 has a section table and a page table, and translates a logical address into a physical address using the section table and the page table. The logical address is composed of a section index part Sx, a page index part Px and an offset,
The logical page address LA is a combination of the section index part Sx and the page index part Px. The logical page address of the instruction currently being executed is LA
It is represented by _n , and the logical page address of the next page is represented by LA _{n + 1} . Also, the physical page address of the instruction currently being executed is represented by PA _n , and the physical page address of the next page is represented by PA _{n + 1} .

When the offset value of the program counter (not shown) reaches a predetermined value, it is checked whether or not the next page is registered in the TLB 9, and if it is not registered, a logic indicating the next page is displayed. The page address is given to the address conversion processing unit 7. Address conversion processing unit 7
Refers to the section table and page table to indicate the next page, the physical page address PA
Find _{n + 1} (synonymous with page frame number PFN).

The TLB register 10 includes a tag section and a logical page.
A part of the address LA, physical page address PA and
And valid bit V are stored. The value of this tag is the logical
Equal to the lower 5 bits of the page address. Effective Bit
V indicates whether the contents of TLB register 10 are valid or invalid.
There is. Tag part (logical page address LA_{n + 1}Lower 5
Bit), logical page address LA_{n + 1}Part of (logical
Page address LA _{n + 1}Except the lower 5 bits of
And the one obtained by the address translation processing unit 7.
Physical page address PA_{n + 1}In the TLB register 10
Stored, and at the same time the valid bit V of the TLB register 10
It is assumed to be 1.

The TLB 9 has a plurality of entries.
Each entry has a tag part, a part of the logical page address LA, and a physical page address PA. The value of the tag part of the top entry is 00, the value of the tag part of the second entry is 01, the value of the tag part of the 16th entry is 15, and the value of the tag part of the 17th entry is 16. ing. Logical page whose lower 5 bits are (00000) ₂
The address is assigned to the entry whose tag part is 00, the lower 5 bits are (00001) ₂ logical page addresses are assigned to the entry whose tag part is 01, and the lower 5 bits are (01111) ₂ logical page addresses are The tag part is assigned to 15 entries, and the lower 5 bits are (1
The logical page address of 0000) ₂ is assigned to the 16 entries in the tag portion. In the logical address part of the TLB entry, the logical page
The address is filled in.

Immediately before the value of the program counter moves to the next page, it is confirmed that the valid bit V of the TLB register 10 is 1, and the content of the TLB register 10 is changed to TL.
At the same time, the _first instruction of the next page is prefetched using the physical page address PA _{n + 1} of the TLB register 10. The contents of TLB register 10 are changed to TLB9
When registered in, the valid bit V of the TLB register 10 is 0
It is said that. When the valid bit V of the TLB register 10 is 0, the prefetch of the first instruction on the next page is TL.
B9.

FIG. 2 is a block diagram of an embodiment of the virtual storage device of the present invention. In the figure, 1 is a program counter, 2 is a +1 circuit, 3 is a comparator, 4 is a control unit, 5 is an address conversion table, 6 is an address conversion arithmetic unit, 7
Is an address conversion processing unit, 8 is a memory, 9 is a TLB, 10
Indicate TLB registers, respectively. program·
The value of the counter 1 is a logical address and is composed of a logical page address LA _n and an offset. The +1 circuit 2 increments the logical page address LA _n stored in the program counter 1. Comparator 3 is +1
The logical page address of the next page output from the circuit 2 is compared with the logical page address of the entry corresponding to the next page in the TLB 9. The comparison result is the signal line S
It is input to the control unit 4 via 1.

The control unit 4 controls the entire system,
For example, it is like microprogram control. It should be noted that the circuit of FIG. 2 may be considered to exist in the storage control unit of the CPU. The contents of the offset portion of the program counter 1 are input to the control unit 4 via the signal line ADR1. When the output of the comparator 3 indicates a mismatch when the value of this offset reaches a predetermined value, the control unit 4 converts the logical page address of the next page and the address conversion processing start instruction via the signal ADR2. It is sent to the processing unit 7.

The address conversion processing unit 7 has an address conversion table 5 and an address conversion arithmetic unit 6. The address conversion table 5 is composed of a section table and a page table. The address translation arithmetic unit 6 performs arithmetic necessary for dynamic address translation, and is different from the arithmetic unit used for instruction processing.
The address conversion table exists in the memory 8.

The TLB 9 has a plurality of entries,
Each entry has a tag part, a logical address part and a physical address part. Numbers such as 00, 01, ..., 15, 16, ... Are written in advance in the tag portion of each entry of the TLB 9. Assuming that the number of entries in the TLB 9 is 32, the value of the tag portion corresponds to the lower 5 bits of the logical page address. For example, an entry whose tag part value is 15 is assigned to the logical page address whose lower 5 bits are (01111) ₂ , and an entry whose tag part value is 16 is the logical page address whose lower 5 bits is (10000) _2.
Assigned to an address. In the illustrated example, the entry corresponding to the page currently being executed is the entry having the tag portion value of 15.

The TLB register 10 stores a tag part, a part of a logical page address, a physical page address and a valid bit V. The address conversion processing unit 7 sends the tag portion, the page portion of the logical page address, the physical page address and the valid bit V of 1 to the TLB register 10 via the signal line ADR3. TLB register 10
Stores these sent data.

The valid bit V of the TLB register 10 is used as a read pointer signal RP indicating a read point. When the valid bit V is 0, the read pointer signal RP1
Becomes 1, and the logical address-physical address conversion is performed using the TLB 9. When the valid bit V is 1, the read pointer signal RP2 becomes 1, and the TLB register 10
Is used to perform the logical address-physical address conversion.

The operation of the apparatus shown in FIG. 2 will be described. The control unit 4 monitors the offset value of the program counter 1 that points to the logical address of the instruction currently being executed, and when it reaches a certain value, adds 1 to the logical page address LA _n of the program counter 1. .. The comparator 3 compares the value of the logical page address of the next page obtained at this time with the value of the logical page address of the entry next to the entry of the TLB 9 indicating the page currently being executed.

If a match is detected as a result of the comparison, it means that the logical page address of the next page is registered in the TLB 9, and the signal S1 is sent to the address conversion processing unit 7 of the logical page address of the next page. Forwarding is suppressed. If the comparison result is a mismatch, the control section 4 sends the logical page address of the next page to the address conversion processing section 7 based on the signal S1, and the DAT processing is performed. At this time, since the address translation processing unit 7 is provided with the dedicated address translation arithmetic unit 6, it is not necessary to stop the instruction processing currently being executed. The logical page address and physical page address pair obtained by DAT is stored in the TLB register 10 through the signal line ADDR3, and at the same time, the valid bit V of the TLB register 10 is set to 1.

When the instructions are continuously executed and the end of the page is detected, the read pointer signals RP1 and RP2 are generated from the valid bit V of the TLB register 10 to obtain the physical address of the next page from the TLB 9 or the TLB 9. It is determined whether to obtain from the register 10. When the DAT of the next page is performed, the valid bit V is 1, so TLB is set.
The read pointer signal RP2 for instructing the register 10 becomes valid, and the first instruction of the next page indicated by this physical page address is prefetched, and at the same time, the information of the TLB register 10 is registered in the TLB 9 through the signal line ADR4. At this time, the valid bit V of the TLB register 10 is set to 0.
To cancel. When the DAT of the next page is not performed, the valid bit of the TLB register 10 remains 0, and the read pointer signal RP for instructing the TLB 9 is read.
When 1 is valid, the prefetch of the first instruction of the next page is performed using TLB9.

[0026]

In general, it is considered that a program is continuous and that instructions are often placed in continuous pages. When the page is changed while the instructions are continuously executed, the instruction DAT generated at this time may delay the execution of the subsequent instructions. According to the present invention, in DAT of consecutive pages, there is no need to wait for instruction processing, and processing efficiency is improved.

[Brief description of drawings]

FIG. 1 is a diagram illustrating an address conversion process during a next page DAT process of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a diagram illustrating a process of converting a logical address to a physical address.

[Explanation of symbols]

 1 Program Counter 2 +1 Circuit 3 Comparator 4 Control Unit 5 Address Conversion Table 6 Address Conversion Arithmetic Unit 7 Address Conversion Processing Unit 8 Memory 9 TLB 10 TLB Register

Claims (3)

[Claims] 1. A virtual memory system in a computer of a virtual memory system having an address translation table for performing a translation between a logical address and a physical address and a TLB for holding a part thereof, which is an instruction of a central processing unit. During the execution, a TLB search is performed in advance for the page next to the page in which the instruction exists, and if a TLB is missed, the dynamic address translation is immediately performed in parallel with the currently executing instruction processing. A virtual memory method characterized by performing. 2. A virtual memory device in a virtual memory computer having an address translation table for performing a translation between a logical address and a physical address and a TLB for holding a part of the address translation table, the page address part and Program counter (1) in which logical address consisting of offset part is set, address conversion table (5) and address conversion arithmetic unit
An address translation processing unit (7) having (6), a TLB register (10) having a logical page address part, a physical page address part and a valid bit, and a pair of a logical page address and a physical page address are written. The control unit (4) includes a TLB (9) having a plurality of registered entries, a +1 circuit (2), a comparator (3), and a control unit (4) for controlling each unit of the device. When the offset value of the program counter (1) reaches a predetermined value, the program is added to the +1 circuit (2).
The logical page address of the next page is obtained by inputting the logical page address of the counter (1), and the TLB
The logical page address of the next page is obtained from the entry corresponding to the next page of (9), and the logical page address of the next page obtained from the +1 circuit (2) and the logical page address of the next page obtained from TLB (9). Compare the address with the comparator (3),
If the comparison result shows a mismatch, the logical page address of the next page obtained from the +1 circuit (2) is used as the address conversion processing unit.
(7) executes the send address conversion process, writes the physical page address and the corresponding logical page address output from the address conversion processing unit (7) to the TLB register (10) and validates the TLB register (10). Check the valid bit of the TLB register (10) when the program counter (1) shows the value immediately before moving to the next page by setting the bit to the value indicating valid.
TLB register when the valid bit indicates valid
The physical page address of (10) is used to prefetch the first instruction of the next page, and the pair of the logical page address and physical page address of the TLB register (10) is set to T.
A virtual memory device, characterized in that it is arranged to perform control for registration in the LB (9). 3. The virtual memory device according to claim 2, wherein the address translation arithmetic unit (6) is an arithmetic unit different from the arithmetic unit for performing instruction processing.