JPS6010336B2 - Address comparison method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for debugging programs, hardware testing, etc. in virtual memory computer systems.
This invention relates to an address comparison method used to stop execution of program instructions at a location specified by an operator and to verify the internal state of a processing system.

In an information processing system that uses the five-sentence memory method,
In order to facilitate the creation of programs, the address space used for programming is separated from the address space used when accessing the main memory using actual hardware.

Therefore, it is necessary to find a correspondence between a logical address and a real address in a page table provided on the main memory, extract the real address, and access the main memory. However, it is inefficient to refer to the above page table for each access. Therefore, in order to speed up the process of finding the correspondence between the logical address and the real address, once the above correspondence has been found, a logical/real address correspondence table (translation) is created in the processing device in the form of a correspondence table. - Lookaside buffer (corresponding to TLB), and the real address corresponding to a given logical address is determined by indexing the LB. In addition, in order to efficiently perform program debugging and hardware testing, virtual memory data processing devices such as those described above are capable of fetching and storing data and commands to locations in the main memory specified by the operator. A function is added to stop the execution of program instructions when a fetch or the like is performed. The circuit means provided for this purpose is unnecessary for the instruction processing inherent in the information processing apparatus, and therefore, it is desirable that the circuit means be as small as possible. However, access requests to the main memory during program execution are made using logical addresses, and then real addresses that are actually used to access memory using hardware, so in addition to converting logical addresses and real addresses, logical It is also necessary to compare the address with the comparison address, which complicates the circuit configuration, which is undesirable from the above-mentioned point of view. The present invention has been made in view of the above points, and its purpose is to provide an address comparison method that makes it possible to reduce the number of circuits applied to control execution stop of instructions during program debugging in a virtual memory data processing system. There is something to do.

The address comparison method of the present invention registers a stored real page address in the address translation table in the address translation table for converting a logical address and a real address, or by a dynamic address translation operation. In the entry of the page table to be used, information indicating that the location specified as the address comparison target exists in the page registered with that entry is stored, and this information is turned on.
, and when the intra-page displacement matches the specified location, the address match condition is sent. Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of an address comparison method according to the present invention.

In the figure, 1 is a TLB (Translation Lookaside Buffer) for address translation that performs high-speed translation from a logical address to a real address, and each entity of this TLBI indicates a part or all of the logical page address LA. part, a part indicating the corresponding real page address RA, and a part setting a flag F indicating that the logical page address LA of the entry matches the logical page address of the comparison target location. There is. Further, 2 is a logical address register, which consists of an upper logical address LA part and a lower intra-page displacement DiSP part, and by accessing TLBI with the logical address LA of this logical address register 2, it corresponds to this. The flags of the real page address RA and the logical page address match are set in the respective selection circuits 3.
and 4 to the real address register 5 and flip-flop 6, respectively. Further, the upper part of the real address register 5 is the real address RA from TLBI, and the lower part is the above-mentioned logical address register 2.
The intra-page displacement DiSP is set respectively, and the real address register 5 is further provided with an incrementer 7 for updating the real address RA.

8 is a comparison circuit to which the intra-page displacement DiSP of the real address register 5 and the address to be compared from the comparison address register 9 are added, and the output of the comparison circuit 8 and An AND gate 10 is connected to the output of the flip-flop 6 for generating an address matching condition.

Reference numeral 11 denotes a page table provided in a main memory (not shown), each entry of which consists of a part indicating a real page address RA, and a part for setting a flag F corresponding to a logical page address that matches the comparison target. The setting of the real page address RA to the page table 11 is performed by the OS (operating system) during paging to the main memory, while the setting of the flag F to the flag field of the page table 11 is performed in the comparison address mode. When the comparison address is previously set, the console processor or the like is used to check the address corresponding to the logical page address that matches the comparison address, and the contents of the page table 11 are converted into DAT (Dynamic Address Translation). TLBI is written during operation. Further, the output side of the real page address section and flag set section in the page table 11 is connected to the bus line 1 to the selection circuits 3 and 4 of the real address register 5 and flip-flop 6.
2 and 13, respectively.
1 real page address RA and address match flag F
directly to real address register 5 and flip-flop 6
It is now possible to output to. Next, the operation of the address comparison circuit of the present invention configured as described above will be explained.

First, the page addresses are compared using the real page address RA set in the page table 11 and the address matching flag F, or the DAT operation is performed.
It is registered in the corresponding fields of B1, that is, the real page address field and flag set field of TLBI, as shown in FIG.

In this state, when a logical address is set in the logical address register 2 for virtual storage access from a processing unit (not shown), the TLBI is accessed by the upper logical address LA. Along with this, the values of real page address RA and flag F corresponding to logical address LA are respectively taken out. As a result, the real page address RA is set in the upper part of the real address register 5 through the selection circuit 3 (assuming that the selection circuit 3 is set to be able to select the address of TLBI at this time).
Furthermore, the intra-page displacement DiSP at the lower level of the logical address register 2 is set at the lower level of the real address register 5. The real page address RA extracted in response to the above access accesses a storage device (not shown). On the other hand, the intra-page displacement DiSP at the lower end of the real address register 5 is transferred to the comparison circuit 8, where it is compared with the address to be compared (designated location) from the comparison address register 9, and if the two match, , a match signal is output from the comparison circuit 8 to the AND gate. At this time, T
If the value of flag F taken out from LBI is "1",
This is applied to the flip-flop 6 through the selection circuit 4, thereby setting a flag, that is, the output of the flip-flop 6 becomes "1", and as a result, the AND gate 10
An address match condition is generated, and the match signal becomes a signal to stop execution of the instruction. Further, if the real page address RA extracted from TLBI by accessing the logical address LA of the logical address register 2 is not the address of the specified location to be compared, only normal address conversion is performed and the address is extracted to the real address register 5. The executed real page address RA continues execution of the instruction by accessing a storage device (not shown).

In addition, if you want to use the real page address or match flag from page table 11 for direct memory access and address comparison due to performance issues, select circuits 3 and 4 select the bus lines 12 and 13 side, and page The real page address RA and match flag F extracted from the table 11 can be registered in the TLBI, and at the same time set in the real address register 5 and flip-flop 6 through the bus lines 12 and 13 and the selection circuits 3 and 4. This shows another embodiment of the present invention in which a flag for page address matching is created and set in the TLB when the contents of a page table are registered in the TLB by a DAT operation.

In the embodiment shown in FIG. 2, the page table 11 is configured to store only the real page address RA, and the upper logical address LA of the logical address register 2 corresponds to the page to be compared in the comparison address register 9. A comparison circuit 14 for comparing comparison addresses is provided, and when a pair of a logical address and a real address is newly registered in the TLBI, the upper logical address L of the logical address register 2 is
A and the comparison address corresponding to the page from the comparison address register 9 are taken into the comparison circuit 14 and compared, and the value of the flag F obtained by the match is set as the flag of TLBI corresponding to the logical address of the designated location. It is designed to be set in the field section. In this embodiment, the same effects as in the case of FIG. 1 can be obtained. Note that in FIG. 2, the parts indicated by the same reference numerals as in FIG. 1 have the same configuration as in FIG. 1, and therefore detailed explanation thereof will be omitted. Regarding the processing of variable-length operands, this is extremely suitable for an information processing apparatus that performs TLB translation of only the operand's first address and thereafter updates and executes only the real address.

As described above, according to the present invention, a real page address is registered in the entry of the page table in which the real page address is registered in the TLB during the TLB or DAT operation for converting the logical address and the real address. stores information indicating that the location specified as the address comparison target exists in the page that is located,
Since this information is used to match the address of the specified location, it is only necessary to prepare registers and address comparison circuits for storing the specified location address for the displacement within the page, reducing the number of circuits. In addition, the present invention has the effect of reducing the size of the circuit for controlling execution stop of instructions when debugging a program in a virtual memory data processing system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of an address comparison method according to the present invention, and FIG. 2 is a block diagram showing another embodiment of the present invention. In the figure, 1 is TLB, 2 is logical address register, 3, 4
is a selection circuit, 6 is a real address register, 6 is a flip-flop, 7 is an incrementer, 8 and 14 are comparison circuits, 9
10 is a comparison address register, 10 is an asode gate, 11 is a page table, and 12 and 13 are bus lines. Figure 1 Figure 2

Claims (1)

[Claims] 1 An entry in an address translation table for converting a logical address and a real address, or an entry in a page table for registering a stored real page address in the address translation table using a dynamic address translation operation. stores information indicating that the address comparison target location exists within the page registered in that entry, and if this information is ON and the intra-page displacement is the address of the address comparison target location. An address comparison method characterized in that an address matching condition is sent when a match occurs.