JP2580587B2 - Address translation buffer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to an information processing system employing virtual memory addressing, and more particularly to an address translation buffer used in an information processing system.

[Conventional technology]

Conventionally, in this type of information processing system, a presence bit indicating presence / absence of a real address in a main memory with respect to a virtual address exists only in a relatively low-speed and large-capacity address conversion table such as a main memory. If the presence bit indicates absence, the virtual address and the real address are not registered in the relatively high-speed address translation buffer on the information processing system.

[Problems to be solved by the invention]

In the conventional information processing system described above, the absence event of the real address detected in the address translation table index can be resolved by some method, that is, the existence of the real address is guaranteed, and the virtual address and the real address are stored in the address translation buffer. After the address pair is stored, it is assumed that access to the virtual address can be performed at high speed by searching for an address conversion buffer.

However, in some types of information processing systems, processing is preempted in order to increase processing capacity. That is, address preparation, operand readout, branch destination instruction fetch, and the like are performed until the execution stage is ready. When the establishment of the branch condition is undecided, preemption is performed in consideration of both the possibility of establishment and non-establishment of the condition, and when the establishment / non-satisfaction is determined, it is common that unnecessary preemption is discarded. is there. At that time, the absence of the real address caused by unnecessary prefetching is not reflected in the processing. Then, the above-mentioned precondition is not satisfied. For example, even if a non-existence event of a real address occurs in prefetching of a branch destination address that does not always branch to a branch instruction in a loop of a program, its reflection is not performed. Since it is not stored in the address translation buffer, the low-speed address translation table is accessed each time (the number of loops), so that there is a disadvantage that execution performance is reduced.

[Means for solving the problem]

An address translation buffer according to the present invention is an address translation buffer used in an information processing system employing virtual memory addressing.
The address translation buffer has an address translation table storing presence bits indicating absence. The address translation buffer stores a partial copy of the address translation table at least in the form of a virtual address, a real address corresponding to the virtual address, and a presence bit. It is characterized by doing.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an information processing system including an address translation buffer according to one embodiment of the present invention.

A virtual address VA from a higher-level device (not shown here) is stored in a virtual address register 1 and an address conversion instruction flag 5 through a signal line 40, and an address conversion instruction is stored in a virtual address register 1 and an address conversion instruction flag 5, respectively. A part of the virtual address register 1 addresses the address translation buffer 2 via a signal line 21, and the virtual address VA contained in the entry is input to the comparison logic circuit 6 via a signal line 23.
At the same time, the contents of the virtual address register 1 are transmitted through the signal line 22, the valid bit V indicating the validity of each entry of the address conversion buffer 2 is transmitted through the signal line 24, and further, the existence of the real address PA corresponding to the virtual address VA is indicated. The existence bits P are input to the comparison logic circuit 6 through the signal lines 25, respectively. The comparison logic circuit 6 determines that the content of the virtual address register 1 matches the virtual address VA from the signal line 23,
Only when the entry indicates that the entry is valid, and when the presence bit P from the signal line 25 indicates that the real address PA exists, the entry corresponding to the given virtual address VA is displayed. Assuming that the real address PA has been registered in the address translation buffer 2, the translation operation ends.

If the above condition is not satisfied, the operation is divided into two cases. Although the virtual address VA matches and the valid bit V indicates that the entry is valid, the existence bit P
Indicates the absence of the real address PA, the real address PA
Is reported to a higher order position via the fault decode logic circuit 7 and the fault register 9 as an absent fault.

If the virtual address VA does not match or the valid bit V indicates that the entry is invalid, the address conversion logic circuit 3
Start The address conversion logic circuit 3 determines an entry of the address conversion table 4 from the contents of the virtual address register 1 and takes in the real address PA, the existence bit P, and the control information C of the entry through the signal lines 30 to 32. The address translation logic circuit 3 examines whether or not a normal translation has been performed based on the content of the fetched entry. If the conversion is normal, the information read from the address conversion table 4 is written to the address conversion buffer 2 through the signal lines 33 to 35. The virtual address that caused the translation operation at the same time
VA is also written to the address translation buffer 2.

At this time, the write address is the address translation buffer 2
Are determined by the same signal line 21 as when indexing is performed. Therefore, the address translation buffer 2 is used for the subsequent translation of the virtual address VA, and the address translation is performed at high speed.

If the address conversion logic circuit 3 detects an illegal conversion, the fault is reported to the host device via the signal line 38 and the fault logic circuit 7 as a fault. At this time, the operation of address conversion is stopped, and writing to the address conversion buffer 2 is not performed. However, when there is no real address, writing is performed. Of course, at this time, the presence bit P is written to indicate absence.

〔The invention's effect〕

As described above, according to the present invention, the absence of a real address detected during address translation is written in a relatively high-speed address translation buffer, thereby pre-fetching the process and performing the real address detection during the address translation. Even when the absence is not necessarily reflected, there is an advantage that the absence of the real address can be detected at a high speed, unnecessary access to the address conversion table is reduced, and a reduction in processing speed can be avoided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an information processing system including an address translation buffer according to one embodiment of the present invention. 1 ... virtual address register, 2 ... address conversion buffer, 3 ... address conversion logic circuit, 4 ... address conversion table, 5 ... address conversion instruction flag, 6 ... comparison logic circuit, 7 ... fault decode logic Circuit 8, real address register 9, fault register 21 to 42 signal line.

Claims (1)

(57) [Claims] 1. An address translation buffer used in an information processing system employing virtual memory addressing, wherein said information processing system includes, in a main memory, a presence bit indicating presence / absence of a real address corresponding to a virtual address. The address translation buffer stores a partial copy of the address translation table with at least the configuration of the virtual address, the real address corresponding to the virtual address, and the existence bit. An address translation buffer, comprising: