JPH0769861B2 - Control method of bypass buffer in cache memory controller - Google Patents

Description

The present invention relates to an address array for storing a copy of addresses in a main memory, a data array for storing a copy of data in a main memory, and a block read from the main memory. The present invention relates to an improvement in a cache memory control device provided with a bypass buffer for temporarily storing data before storing it in a data array, and more particularly to a control method for the bypass buffer.

[Conventional technology]

As one method of the cache memory control device, one block (for example, 64 bytes) of data can be stored in addition to an address array that stores a copy of the address of the main memory and a data array that stores a copy of the data of the main memory. By providing a bypass buffer having a capacity, the block read data returned from the main storage device in response to a block read request at the time of a miss is temporarily stored in the bypass buffer, and there is a free space for subsequent block read requests. A method is known in which the block read data stored in the bypass buffer is transferred to the data array by utilizing time or the like, thereby making it possible to speed up the processing.

By the way, a conventional cache memory control device provided with a bypass buffer has a comparison circuit for comparing a block address of a store request for instructing an update of data with a block address of data stored in the bypass buffer. When the comparison circuit detects a match between the two at the time of request, after transferring all the data stored in the bypass buffer to the data array, the store processing is performed in the data array. The data array is updated in units of processing data width between the arithmetic unit and the cache memory, for example, in units of 8 bytes. Further, the update of the data array is not performed immediately when a store request instructing the update is made, but the store address which is the update information of the address array is stored in the store address buffer and the update data is sent later. The data is stored in the store data buffer, and the data array is updated using the stored store data and store address. That is, when there is a store request to update the data stored in the bypass buffer, the data stored in the bypass buffer is transferred to the data array, and the store address and store data are stored in the store address buffer and the store data buffer. After is stored, the data will be updated in the data array.

Further, the conventional cache memory control device has a comparison circuit for comparing the block address in the output of the store address buffer for temporarily storing the store address with the block address of the subsequent read request. If the circuit detects a match between the two, that is, if the block containing the read request target address is undergoing store processing, the read operation is performed until the store processing for the block containing the read request target address ends. I'm trying to make the process wait.

[Problems to be solved by the invention]

Therefore, in the above-described conventional cache memory control device, when the block including the address to be the store request is stored in the bypass buffer, the data stored in the bypass buffer is transferred to the data array. , There was a problem that had to wait for store processing. Further, in the above-mentioned conventional example, there is a store request for the data stored in the bypass buffer, and the address which is the target of the store request is included during the store processing by this store request. When there is a read request for a block, data is transferred from the bypass buffer to the data array, regardless of whether or not the address targeted for the read request is in the process of storing, and until the store process ends, There was also the problem of having to wait for a read request.

The present invention solves the above-mentioned problems, and an object of the present invention is to speed up the store processing and to speed up the processing when a read request is made to an address in a block including data being stored. It is to be able to realize.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention stores a data array for storing a copy of data in a main storage device, and temporarily stores block read data from the main storage device before storing it in the data array. In a cache memory control device including a bypass buffer, at the time of a read request or a store request, it is detected whether or not a block including an address to be the target of the read request or the store request is stored in the bypass buffer. When the detecting unit detects that the block including the target address of the store request is stored in the bypass buffer, the storing process is performed to the bypass buffer, and the detecting process is not performed. Is a store processing means for performing store processing on the data array, and the bypass buffer. A bypass control buffer having an entry corresponding to each entry of the bypass buffer, and each entry stores a bypass buffer store wait flag indicating whether or not the data stored in each entry of the bypass buffer is store processing; And the detection means detects that the read request is directed to the bypass buffer, thereby setting the bypass buffer store wait flag stored in the entry of the bypass control buffer corresponding to the address of the read request. If the bypass buffer store wait flag is OFF, the data is read from the bypass buffer and returned to the request source of the read request, and if it is ON, the read request is made to wait until the store processing for the bypass buffer is completed. It is the one.

[Work]

In each entry of the bypass control buffer, a bypass buffer store wait flag indicating whether or not the data of the corresponding entry of the bypass buffer is being stored is stored. Further, when a read request is made for the data stored in the bypass buffer, if the bypass buffer store wait flag stored in the entry of the bypass control buffer corresponding to the address of the read request is on, the read request is kept waiting and turned off. In this case, the data is read from the bypass buffer and returned to the request source of the read request.
Therefore, even if the block including the address being stored is the same as the block including the address that is the target of the read request, the read process is immediately executed if the address itself is different. Further, when the block including the address for which the store request is made is stored in the bypass buffer, the store processing means directly performs the store processing on the bypass buffer.

〔Example〕

 Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, the request register 10 indicates the type of access request,
It is a register that holds address information composed of a request code part including instruction contents and validity, and an address part of an access request. The address part of the address information is
Further, it is divided into a key address, a set address, and an in-block address, a block address is composed of the key address and the set address, and a data array address is composed of the set address and the in-block address. The request code portion of the address information held in the request register 10 is connected to the control circuit 70 by the connection 107.
The control circuit 70 decodes the request code, generates a control signal necessary for each unit, and distributes the control signal. Also,
The address portion of the address information is input to the switching circuit 65 by the connection 103 and becomes the main storage request address. Furthermore,
The key address in the address part is input to the address array 20 and the detection circuit 21 via a connection 102, the set address is input as a reference address of the address array 20 via a connection 101, and the in-block address is connected to a store address buffer 31 via a connection 105. And detection circuit 35 and bypass buffer
51 and the control buffer 50 holding the control information of the bypass buffer 51, the block address is input to the store address buffer 31, the detection circuits 34 and 35, the register 52 and the detection circuit 53 by the connection 106, and the data array address. Is input to the data array 40 through the connection 104, the switching circuit 66, and the connection 661.

An address array 20 storing a copy of an address of a main memory (not shown) and a validity indicating bit indicating whether or not the copy of the address is valid is read at a set address of connection 101 and read to connection 202. When the validity indication bit is valid and the address read from the address array 20 to the connection 201 and the key address of the request register 10 match, the detection circuit 21 is called a found block.
Turns on a fund block signal (hereinafter referred to as an FDB signal) on the connection 211 to notify the control circuit 70 that the target data exists in the cache memory control device.

The block address obtained by combining the key address and the set address of the request register 10 is input to the detection circuit 53 by the connection 106, and the register that holds the block address of the data stored in the bypass buffer 51 here.
The match between the output of 52 and the entry valid bit of the bypass buffer 51 (hereinafter referred to as the BEV bit) held in the bypass control buffer 50 for each entry is checked to see if the BEV bit is turned on. When the block address match is detected, the bypass buffer match signal (hereinafter referred to as the BBM signal) on the connection 531 is turned on to notify the control circuit 70.

When the request register 10 accepts the read request, the control circuit 70 checks the FDB signal and the BBM signal, and basically executes the following processing.

When the FDB signal is off, since the data corresponding to the read request does not exist in the cache memory control device, the control circuit 70 sends the block read request as the main memory request code and the switching circuit 65 requests the request register 10 The contents of the address part of the above are sent to the main storage device as the main storage request address. On the other hand, until the main memory read data is returned, the contents of the request register 10 are held as they are, and the key address and block address of the request register 11 are respectively supplied to the entry of the address array 20 and the register 52 via the connection lines 102 and 106. If there is valid data in the bypass buffer 51, the output of the register 52 is selected by the switching circuit 66, and the switching circuit 64 and the connection 641 are connected to the data array 40 that stores a copy of the data in the main memory. Then, the data in the bypass buffer 51 is transferred via the switching circuit 61. The data transfer to the data array 40 is executed by using the period until the first main storage read data is returned. The block read is a transfer request for one block of the main memory,
In the present embodiment, the size is 64 bytes, and the data transfer width with the main memory is 8 bytes, so a total of 8 main memory read data are returned. The first main memory read data is registered in the bypass buffer 51 via the switching circuit 63, and at the same time returned to the request source as reply data via the switching circuit 64 and the switching circuit 62. Are stored only in the bypass buffer 51.

Next, when the FDB signal is on, it indicates that the data corresponding to the read request accepted by the request register 10 exists in the cache memory control device. In this case, the control circuit 70 refers to the BBM signal, and when the BBM signal is off, the data read from the data array 40 by the data array address on the connection 104 is returned to the request source via the switching circuit 62, and the BBM signal is sent. When the signal is on, since the data obtained by the block load is not in the data array 40 and remains in the bypass buffer 51, the data read from the bypass buffer 51 by the address in the block by the connection 105 is the switching circuit 64, Returned to the requestor via 62.

The outline of the read request processing is as described above, and further, the processing when a read request occurs during the processing of the store request is slightly complicated unlike the above. This will be described below.

When the store request is accepted by the request register 10, the block address and the in-block address are stored in the store address buffer 31 by the connections 105 and 106, and the control circuit 70 stores the store form information obtained by decoding the request code section and the store buffer entry. The validity bit (hereinafter referred to as the SAV bit) indicating the validity of is stored in the store control buffer 30 via the connection 301. At this time, the SAV bit is registered as ON, and is turned OFF when the store request processing described below is completed.

Store address buffer 31 for the address of the above store request
When the store data (8 bytes) prepared by the operation executing unit and the store mask indicating whether or not the byte unit store can be executed are sent after the registration to the store data buffer 33 and the store data buffer 33, respectively. It is registered in the mask buffer 32. Then, after that, the store control buffer 30, the store address buffer 31, the store mask buffer 32, and the store data buffer 33 are simultaneously read out, and the store control buffer
The read data of 30 is sent to the main memory as a main memory request code, and the output of the store address buffer 31 is the connection 31
3, sent as the main memory request address via the switching circuit 65, the output of the store mask buffer 32 is sent as the main memory store mask, and the output of the store data buffer 33 is sent as the main memory store data. Also, when the store request is made and the FDB signal of the detection circuit 21 is turned on, the BBM of the detection circuit 53 is
When the signal is off, that is, when the requested store address is one address in the block existing in the data array 40, the update of the data stored in the data array 40 with the store data is executed. Further, when the store request is made and the FDB signal of the detection circuit 21 is turned on, B of the detection circuit 53 is
When the BM signal is on, that is, when the store-requested address is one address in the block existing in the bypass buffer 51, it is stored in the bypass buffer 51 according to the data array address output to the connection line 314. The stored data is updated with the stored data.

On the other hand, the detection circuit 34 also receives the block address in the store address buffer 31 via the connection 311, and when there is a read request, the same block as the block including the read-requested address is undergoing store request processing. A circuit that detects whether or not there is a detection circuit 35
The block address is input from the store address buffer 31 via the connection 311 and the in-block address is input via the connection 312, and when there is a read request, the same address as the read-requested address is being stored. It is a circuit that detects whether or not there is.
In the present embodiment, the detection circuit 35 detects whether or not the target address of the read request is stored in the store address buffer 31, so that appropriate read request processing during store processing becomes possible as described later.

As described above, since the processing of the store request cannot be completed immediately, in the processing of the subsequent read request, it is determined whether or not there is a store request that is being processed for the same address. Therefore, appropriate control is required. In the present embodiment, as described above, the data processing width is in units of 8 bytes, and one block is 64 bytes.
That is, each entry of the store data buffer 33, the data array 40, and the bypass buffer 51 has a length of 8 bytes, and the bypass buffer 51 is composed of 8 entries.

The request code in the request register 10 contains 8
The all-write flag indicating that all 8 bytes have been written to the byte boundary is included.
This flag is registered in the store control buffer 30 at the same time as the SAV bit. When this full write flag is on, all 8 bytes of store data sent from the operation execution unit are finally stored in the data array 40, and when the full write flag is off, the specified data specified by the request code unit is specified. Of bytes of store data are partially written to the data array 40. In addition, in response to a read request to be described later, the detection circuit 34 detects whether a store request for the same block is being processed for each entry of the store address buffer 31, and a store request for the same 8 bytes is being processed. Whether or not there is is detected by the detection circuit 35.

In the detection circuit 34, address matching and SAV
The bit is judged, and the result is sent to the control circuit 70 for each entry by the connection 341, and the control circuit 70 creates a logical sum of the coincidence for each entry. This logical sum is called a store block address match signal (hereinafter referred to as BAM signal),
When this BAM signal is on, it indicates that an address with a block including the read-requested address is being stored. Similarly, the logical sum of the results detected by the detection circuit 35 and notified by the connection 351 is called a store data array address match signal (hereinafter referred to as the CAM signal), and when this CAM signal is on, the read-requested address Indicates that it is in the process of storing itself.

On the other hand, when processing the store request, when the detection circuit 53 notifies the store request to the block stored in the bypass buffer 51 by turning on the signal BBM, the control circuit 70 responds to the address in the block. The bypass buffer store wait flag (hereinafter referred to as the BSW flag) included in the entry of the bypass control buffer 50 is registered as ON. This BSW flag is referenced via the connection 501 in the processing of the read request, and when the BBM signal is on,
If the BSW flag is on, the reading of the bypass buffer 51 is delayed, and if the BSW flag is off, the bypass buffer 5 is immediately returned.
1 is read. The above processing is controlled in more detail by the above-mentioned BAM signal, CAM signal and FDB signal. Hereinafter, how to process the read request by each signal will be described.

(1) When the FDB signal is off (that is, when the read-requested address does not exist in the cache memory controller. In this case, the BBM signal and the BSW flag are always off due to the structure). The BAM signal is off. In the case (that is, when the read-requested address does not exist in the store address buffer 31), in this case, the control circuit 70 sends a block read request to the main memory device according to the procedure described above, and the data returned from the main memory device Data of the address corresponding to the read request is returned to the request source via the switching circuits 63, 64, 62.

When the BAM signal is on (that is, when an address with a block including the read-requested address is stored in the store address buffer 31) In this case, the CAM signal is turned on and off to perform the following two methods. Be divided.

(I) When the CAM signal is on and the all write flag in the store control buffer 30 of the entry that caused it is on,
The control circuit 70 stores the store data in the store data buffer 33.
Then, the store request is sent to the main storage device, and at the same time, the store data received in the store data buffer 33 is returned to the request source via the switching circuit 62. At this time,
The block read request to the main memory is not made, and the data can be returned at high speed.

(Ii) When the CAM signal is off, it means that another address of the block including the read-requested address is stored in the store address buffer 31.
The control circuit 70 receives the store data in the store data buffer 33, sends a store request to the main memory device, further sends a block read request to the main memory device, and responds to the read request from the returned main memory read data. The address data is returned to the request source via the switching circuits 63, 64, 62.

(2) When the FDB signal is on (that is, when the block of the read-requested address exists in the cache memory control device) When the BAM signal is off (that is, the read of the blocks stored in the address array 20) If the block that is the target of the request is not stored (in this case, there is no entry with the BSW flag on by structure) In this case, if the BBM signal is on, that is, the block requested to be read is stored in the bypass buffer 51. When it remains, the data read from the bypass buffer 51 is returned to the request source via the switching circuits 64 and 62. Also, BBM
If the signal is off, the data is read from the data array 40 and returned to the request source via the switching circuit 62.

When the BAM signal is on (that is, when the block that is the target of the read request among the blocks stored in the address array 20 is undergoing store processing) (i) When the BBM signal is on and the SBW flag is off ( That is, when the block including the read-requested address is in the bypass buffer 51, but the read-requested address itself is not the target of the store request processing), the data read from the bypass buffer 51 by the in-block address is switched. Return to the requester via the circuits 64 and 62.

(Ii) When the BBM signal and the BSW flag are both on (that is, when the block including the read-requested address is in the bypass buffer 51 and the read-requested address itself is the target of the store request processing) ), The corresponding store data is the store data buffer
The read request process is kept waiting until it is registered in 33. Then, all write flags in the corresponding store control buffer 30 are checked, and if all write flags are on, switching is performed when the corresponding store data is written from the store data buffer 33 to the bypass buffer 51 via the read switching circuit 63. The store data is returned to the request source via the circuit 62. If the all write flag is off, the store data in the store data buffer 33 is partially written to the bypass buffer 51 via the switching circuit 63, and then the data read from the bypass buffer 51 is returned to the request source.

(Iii) When the BBM signal is off (that is, when the read-requested address is not in the bypass buffer 51),
If the CAM signal is off, the data is read from the data array 40 and immediately returned to the request source. If the CAM signal is on,
If the all write flag of the entry of the cause is on, after accepting store data in the store data buffer 33,
The output of the store data buffer 33 is written to the data array 40 via the connection 331 and the switching circuit 61, and at the same time the store data is returned to the request source via the switching circuit 62. If the all write flag is off, the store data buffer 33 After partially writing the output of the above into the data array 40, the data array 40 is returned to the read request source.

〔The invention's effect〕

As described above, according to the present invention, at the time of a store request, if the block including the address that is the target of the store request is stored in the bypass buffer, the store process is performed on the bypass buffer. Therefore, compared to the conventional example in which the data stored in the bypass buffer is transferred to the data array, there is an advantage that the store processing can be speeded up. Further, according to the present invention, a bypass control buffer having an entry corresponding to each entry of the bypass buffer, in which each entry stores a bypass buffer store wait flag, is provided when a read request for data stored in the bypass buffer is made. When the bypass buffer store wait flag is on, read processing is provided, and when it is off, data is immediately read from the bypass buffer and returned to the request source of the read request. Even if the containing block and the block containing the address that is the target of the read request are the same, the read process can be executed immediately if the address itself is different, so the processing of the read request following the store request is speeded up. There are advantages.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, 20 …… address array, 21,34,35,53 ……
A detection circuit, 31 ... Store address buffer, 33 ... Store data buffer, 40 ... Data array, 51 ... Bypass buffer, 70 ... Control circuit.

Claims (1)

[Claims] 1. A cache memory comprising: a data array for storing a copy of data in a main memory; and a bypass buffer for temporarily storing block read data from the main memory before storing in the data array. In the control device, at the time of a read request or a store request, a detection unit that detects whether or not a block including an address to be the target of the read request or the store request is stored in the bypass buffer, and the detection unit. If it is detected that the block including the address that is the target of the store request is stored in the bypass buffer, store processing is performed on the bypass buffer, and if not detected, it is stored in the data array. Store processing means for performing processing, and an entry corresponding to each entry of the bypass buffer And a bypass control buffer in which each entry stores a bypass buffer store wait flag indicating whether or not the data stored in each entry of each bypass buffer is undergoing store processing, When it is detected that the read request is for the bypass buffer, the bypass buffer store wait flag stored in the entry of the bypass control buffer corresponding to the address of the read request is referred to If the wait flag is off, data is read from the bypass buffer and returned to the request source of the read request, and if on, the read request is waited until the store processing for the bypass buffer is completed. Control of bypass buffer in controller method.