JPS62174846A - Storage checking system - Google Patents

Abstract

PURPOSE:To accelerate the execution of read processing and to quickly read data by bypassing data in a storage buffer under the prescribed conditions so as to return it to a request source if preceding storage processing is not terminated at the time of requesting read. CONSTITUTION:Storage checking system is comprised of a request register 10, an address array 20, a detection circuit 21, a storage control buffer 30, a storage address buffer 31, a storage mask buffer 32, a storage data buffer 33, detection circuits 34 and 35, a data array 40, a bypass buffer control buffer 50, a bypass buffer 51, a block address register 52, a detection circuit 53, switching circuits 61-66 and a control circuit 70. If the preceding storage processing is not terminated at the time of requesting read, data in the storage buffer is bypassed and returned to the request source.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a store check method, and particularly to a store check method in an information processing apparatus having a cache memory.

[Conventional technology]

Conventionally, this type of information processing apparatus has not had a determination circuit that determines whether the contents registered in the store buffer exist in the cache memory. Therefore, when a read request occurs, the read address is compared with the store address registered in the store buffer, and if they match, the read process is stopped and all the store data corresponding to the store address registered in the store buffer is Registering in the store buffer and writing from the store buffer to the cache memory and main storage device are performed with priority, and when the empty state of the store buffer is detected, the stopped read process is restarted.

[Problem that the invention seeks to solve]

The conventional store check method described above always waits for the write of store data to the cache memory or main storage device to be completed when a store check occurs before executing the subsequent read process, so there is a drawback that the performance drop due to the store check is significant. .

In view of the above-mentioned points, an object of the present invention is to bypass the data in the store buffer and return it to the request source under predetermined conditions when the preceding store process has not been completed at the time of a read request. An object of the present invention is to provide a store check method that speeds up the execution of read processing and enables high-speed data reading.

[Means for solving problems]

The store check method of the present invention is provided in an information processing device having a cache memory, including a store buffer capable of holding multiple entries of write addresses to the main memory and cache memory and write data corresponding to the write addresses, and a store control buffer that holds a full write flag indicating that it is a write; a group of validity display bits that display the validity of the store buffer for each entry; and processing data between the arithmetic unit and the cache memory. address coincidence detection means for detecting, in units of width, a coincidence between a main memory read address of a read request and a write address of an entry that is indicated as valid by the validity indicating bit group in the store buffer;
When the main memory read address exists in the cache memory, the read request is made to wait until the store data in the store buffer can be stored in the cache memory and bypassed at the same time in response to a match output from the address match detection means. , when the main memory read address does not exist in the cache memory, the store data in the store buffer is sent to the main memory according to the match output from the address match detecting means and the all write flag, and at the same time bypassing is performed. After making the read request wait until the read request is completed or storing the store data in the store buffer in the host tC device, 11;
and control means for controlling whether to send the read request to the I-article storage device.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

The figure is a block diagram showing one embodiment of the present invention.

The store check method of this embodiment uses a request register (hereinafter abbreviated as RQR>10) and an address array.
(hereinafter abbreviated as AA) 20, a detection circuit 21,
Store control buffer (hereinafter abbreviated as SCB) 30 and store address buffer (hereinafter abbreviated as SAB)
31, a store mask buffer 32 (hereinafter abbreviated as SMB), a store data buffer (hereinafter abbreviated as SDB) 33, detection circuits 34 and 35, and a data array (hereinafter abbreviated as DA) 40. , a bypass buffer control circuit (hereinafter abbreviated as BCB) 50, a bypass buffer (hereinafter abbreviated as BB) 51, a block address register (hereinafter abbreviated as BAR) 52, a detection circuit 53, and a switching circuit. It is composed of circuits 61 to 66 and a control circuit 70.

AA20 and DA40 constitute Cassonyu memory, and 5
AB31, 5MB52, and 5DB33 constitute a store buffer.

RQRIO is a register that holds a request code section including the type of access request, instruction content, and validity, and an address section of the access request.

AA20 is an address section of a cache memory that stores the correspondence between blocks registered in DA40 and blocks in the main storage device.

The detection circuit 21 detects whether the cache memory address (signal line 201) issued by AA20 matches the key address (signal line 102) in RQRlo and the AA20
Validity display bit (hereinafter abbreviated as V bit) that indicates the validity of the entry registered in the field (signal line 202)
This is a circuit to investigate.

5CB30 is a buffer that stores store type information and the ■ bit indicating the validity of the entry in 5AB31.

5AB31 is the block address and DA in the block.
This is a buffer for registering addresses.

5MB 52 is a buffer that registers a store mask indicating whether or not store execution is possible in units of bytes sent from the arithmetic execution unit.

The 5DB 33 is a buffer that registers store data sent from the calculation execution unit.

The detection circuit 34 detects 5AB3 in response to a subsequent read request.
This circuit detects whether a store request for the same block is being processed in each entry unit.

The detection circuit 35 detects the same 8
This circuit detects whether a store request for a byte boundary is being processed.

DA40 is a data section of a cache memory that stores data.

The BCl 350 is a buffer that holds a bypass buffer store wait flag and the like for controlling the BB 51.

BB51 is a buffer for registering main memory read data.

BAR52 is a register that holds the block address of the block registered in BB51.

The detection circuit 53 receives the block address (
In addition to detecting a match between the signal line 106) and the block address held in the BAR 52, the entry valid pinpoint (
This is a circuit that checks the REV bit (hereinafter abbreviated as the REV bit).

The switching circuits 61 to 66 are circuits that switch data or addresses.

The control circuit 70 is a circuit that controls each section shown in the figure and sends a main memory request code to the main memory device.

In this embodiment, the data processing width is 8 bytes, and one block is 64 bytes. That is, 5DB33
, DA40, and BB51 are 8 bytes long, and BB51 is composed of 8 entries.

Next, the operation of the store check method of this embodiment configured as described above will be explained.

The output of the request code part of RQRIO is signal line 107
The request code is sent to the control circuit 70 via the request code, and the request code is decoded and necessary control signals are generated and distributed to each section shown in the figure. Further, the output of the address section of RQRIO is distributed to each section shown in the figure via signal lines 101 to 106 as necessary.

AA20 is read by the set address (signal line 101), and the read address is read by the detection circuit 21 as RQRlo.
A match with the key address (signal line 102) within is detected. In addition, in the detection circuit 21, a ■ bit (signal line 202) that indicates the validity of the entry stored in the AA 20
can be investigated. When the key addresses match and the V bit is on, the found block signal (hereinafter abbreviated as FDB signal) on the signal line 211 is turned on and the control circuit 70 is informed that the target data exists in the cache memory. You will be notified that

The block address (signal line 106), which is a combination of the key address and set address from RQRlo, is detected by the detection circuit 53 to match the block address output from the BAR 52. In addition, in the detection circuit 53, BCB5
The BEV bit held in each entry of BB51 in 0 is examined. Block address lost and BEV
When bit 7 is on, a bypass buffer match signal (hereinafter abbreviated as BBM signal) is sent via the signal line 531.
is notified to the control circuit 70.

When a read request is accepted to RQRIO, the control circuit 70 checks the FDB signal and the BBM signal.

When the FDB signal is off, a block read request is sent to the main storage device. On the other hand, until the main memory read data is returned, RQRIO is held as is, and RQRIO is stored in the entry of AA20 and BAR52.
In addition to registering the key address (signal line 102) and block address (signal line 106) in QRIO, if valid data exists in BB51, DA4
Transfer data to 0.

The data is transferred to the DA 40 using the period until the first main memory data is returned.

A block read request is a request to transfer one block of the main memory. In this example, one block is 64 bytes in size, but since the data transfer width with the main memory is 8 bytes, the main memory read request is a request to transfer one block of the main memory. Data is returned eight times.

The main memory read data returned the first time is sent to the switching circuit 63.
The data is registered in the BB 51 via the switching circuits 64 and 62 and sent back to the request source as reply data. The main memory read data returned from the second time onwards is
Registered on BB51.

If the FDB signal is on, the BBM signal is further referenced. When the BBM signal is off, data read from the DA 40 at the DA address (signal line 104) is sent back to the request source as reply data via the switching circuit 62. When the BBM signal is on, data read from the BB 51 at the intra-block DA address (signal line 105) is sent back to the request source as reply data via the switching circuit 62.

The outline of read request processing is as described above, but in addition, if a store request that is being processed remains in the store buffer and the area of that store is the same as the area of the read request, the store request that is being processed will be Processing of a read request may be delayed until processing of the request is completed.

When a store request is accepted to RQRIO, the block address (signal line 106) and DA address within the block (
The store format information decoded by the control circuit 70 and the V bit (hereinafter abbreviated as SAV bit) indicating the validity of the store buffer entry are registered in the 5CB30. At this time, SA
The V bit is registered as on, and is turned off when the following store request processing is completed.

After registering the address of the store request, the arithmetic execution unit sends store data (8 bytes) and a store mask indicating whether or not the store can be executed in units of bytes.
and 5MB52, respectively.

After this, 5CB30.5AB31.5MB52 and 5
DB33 is read at the same time, the output from 5CB30 is the main memory request code, the output from 5AB31 is the main memory request address, the output from 5MB52 is the main memory store mask, and the output from 5DB33 is the main memory store. Each data is sent to the main storage device, and the store request processing ends.

If the FDB signal is on at the time of a store request, writing of store data to the DA 40 is executed prior to sending the store request to the main storage device.

If there is a store request to the same area, processing of the read request is made to wait until the processing of the store request is completed.

When processing a store request, the store request address is BB.
The detection circuit 53 checks whether the detected data corresponds to the block above 51, and the control circuit 70 is notified by the BBM signal. When the BBM signal is on, one block of data is transferred from the BB51 to the DA40 prior to processing the store request, and then the store request is processed and transferred to the DA40.
The data on the main storage device 40 are controlled so that there is no mismatch between the data on the main storage device and the data on the main storage device.

Since the processing of a store request cannot be completed immediately, in processing a subsequent read request, it is necessary to control the subsequent read request by determining whether there are any remaining store requests being processed for the same area. It won't happen. .

The request code section in RQRIO includes an all write flag indicating that all 8 bytes are written to an 8 byte boundary, and the all write flag is registered in 5CB30 at the same time as the SAV bit when processing a store request. . The detection circuit 34 detects whether or not a store request for the same block is being processed for each entry of 5AB31 in response to a subsequent read request. Further, the detection circuit 35 detects whether or not a store request for the same 8-byte boundary is being processed in response to a subsequent read request.

The detection circuit 34 determines whether the address matches each entry and whether the SAV bit is on or off, and sends the result to the control circuit 70 for each entry via the signal line 341. Creates a logical OR of matches on an entry-by-entry basis. This OR signal is called a store block address match signal (hereinafter abbreviated as RAM signal).

Similarly, the logical sum detected from the detection circuit 35 is stored in D
A address match signal (hereinafter abbreviated as CAM signal)
It is called.

When processing a store request, if the detection circuit 53 detects that the store is for a block registered in the BB 51, the bypass buffer store included in the entry of the BCB 50 corresponding to the DA address in the block is detected. Wait flag (hereinafter abbreviated as BSW flag)
Register as on.

The BSW flag is referenced in the processing of a read request. If the BSW flag is on when the BBM signal is on, reading of BB51 is made to wait, and if the BSW flag is off, reading of BB51 is performed immediately.
51 is read out.

The above-mentioned processing is performed on the above-mentioned RAM signal, CAM signal and F
Further detailed processing is performed in response to the DB signal.

(When the IIFDB signal is off. In this case, the BBM signal and BSW flag are always off.

(1-1) When the BAM signal is off, a block read request is sent to the main memory, data is read from the main memory, and is returned to the request source.

(1-2) When the RAM signal is on, store data is accepted in the 5DB33, read requests are made to wait until the store request is sent to the main storage, and block read requests are sent to the main storage after the store request is sent. The read data is sent back to the request source. However, if the CAM signal is on and all write flags in 5CB30 of the entry that caused it are on, the store data will be transferred to 5DB3.
3, the store request is sent to the main storage device, and at the same time, the store data is sent back to the request source via the switching circuit 62. Therefore, there is no need to request a block read to the main memory, and data can be returned at high speed.

When the f21FDB signal is on (2-1) When the RAM signal is off In this case, B
There are no entries with the SW flag on.

If the BBM signal is on, data is read from the BB51 and sent back to the request source. If the 133M signal is off,
Data is read from the DA 40 and sent back to the request source.

(2-2) When the BAM signal is on If the BBM signal is on and the BSW flag is off, data is read from the BB51 and sent back to the request source. If the BBM signal is on and the BSW flag is on, the processing of the read request is delayed until the corresponding store data is registered in the 5DB 33, and all write flags in the corresponding 5CB 30 are checked.

If the all write flag is on, the switching circuit 62 reads the store data from the 5DB33 and writes it to the BB51.
The store data is sent back to the requester via .

If the full write flag is off, after partially writing the store data output from 5DB33 to BB51,
The data read from 51 is returned to the request source. BBM
If the signal is off and the CAM signal is off, the DA40
The data is read from the server and immediately sent back to the requester. CA
If the M signal is on and the all write flag of the entry for that factor is on, after accepting the store data in the 5DB 33, the store data from the 5DB 33 is written to the DA 40 and at the same time is bypassed and returned to the request source. If the all write flag is off, the output of 5DB33 is DA4
．． After partially writing to 0, the data is read from the DA 40 and sent back to the request source.

〔Effect of the invention〕

As explained above, the present invention includes a store buffer, a store control buffer that holds all write flags, a validity display via) group, and an address match detection that detects a match between a main memory read address and a write address. By providing a means and a control means for controlling the store data to be bypassed and returned to the request source based on these, if the preceding store processing has not been completed at the time of a read request, the data in the store buffer is By bypassing the data and returning it to the request source, there is an effect that data reading after all writing can be processed at high speed.

[Brief explanation of drawings]

The figure is a block diagram showing one embodiment of the present invention. In the figure, 10...request register, 20...address array, 21.34, 35.53...detection circuit, 30...
...Store control buffer, 31...Store address buffer, 32...
・Store mask buffer, 33...Store data buffer, 40...Data array, 50...Bypass buffer control buffer, 51...
. . . Bypass buffer, 61 to 66 . . . Switching circuit, 70 . . . Control circuit.

Claims (1)

[Scope of Claims] An information processing device having a cache memory, comprising: a store buffer capable of holding a plurality of entries of a write address to a main storage device and a cache memory, and write data corresponding to the write address; a store control buffer that holds an all-write flag that indicates that there is a write flag; a group of validity display bits that display the validity of the store buffer for each entry; and a processing data width unit between the arithmetic unit and the cache memory. address matching detection means for detecting a match between a main memory read address of a read request and a write address of an entry that is indicated as valid by the validity indicating bit group in the store buffer; If the store data exists in the memory, the store data in the store buffer is stored in the cache memory in response to a match output from the address match detection means, and at the same time the read request is made to wait until the data can be bypassed. If the data does not exist in the cache memory, the store data in the store buffer is sent to the main storage device according to the match output from the address match detection means and the all write flag, and at the same time, the read request is made to wait until the data can be bypassed. or a control means for controlling whether to send the read request to the main storage device after storing the store data in the store buffer in the main storage device. .