KR970010367B1 - On-board interleaving apparatus and method of main memory on multi processor system - Google Patents

Abstract

The first and second input buffers(21a,21b) work as each data course to store in the first and second banks(23,24) the relevant address and data stored temporarily to input a queue(18) according to I/O signal in the RP standard interface(17) to be connected to system bus. The first and second output buffer(22a,22b) act as each data course for extra storage to output each extra address and data to RP standard interface(17) through output queue(19) to output the relevant address and data read from the first and second bank(23,24) to PR standard interface(17) through output queue(19). The first memory control part(20a) and the second memory control part(20b) control selectively the first input buffer(21a) or the first output buffer(22a) and the second input buffer(21b) or the second output buffer(22b).

Description

On-board Interleaving Device and Method of Main Memory in Multiprocessor System

1 is a block diagram of a typical TICOM.

2 is a block diagram illustrating an address path of a conventional memory board.

3 is a block diagram of a conventional interleaving related addresser path.

4 is a block diagram illustrating a data path of a conventional memory board.

5 is a block diagram illustrating a data path of a memory board of the present invention.

6 is a block diagram for an interleaving related address path of the present invention.

7 is an in-board interleaving flowchart of main memory in the multiprocessor system of the present invention.

FIG. 7A is an interleaving flowchart when the input queue is designed to correspond to the number of banks. FIG.

7B is an interleaving flowchart when sharing input queues.

* Explanation of symbols for main parts of the drawings

17: RP standard interface 18: input queue

19: output queue 20a: first memory controller

20b: second memory controller 21a: first input buffer

21b: second input buffer 22a: first output buffer

22b: second output buffer 23: the first bank

24: Second Bank

The present invention relates to an on-board interleaving apparatus and method of a main memory in a multiprocessor system, and more particularly, to improve the performance of a system by implementing interleaving in a memory board of a main memory of a bus-based computer system.

In general, a TCOM (Tightly coupled multi-processor) is a system that can carry up to 20 processors based on a bus as the main computer II as shown in FIG. (1), an SCM (Small Core Memory) 2, a memory 3, an input / output processor 5 for processing input / output data of the VME bus 6, the input / output processor 5 and the central processing It consists of a system bus 4 connecting the device 1, the SCM 2 and the memory 3.

The interleaving requires that memory modules operate independently of each other in order for a program to have a locality (locality), so that the program can quickly access the continuous memory.

Thus, the least significant bit of the address is typically adjusted to vary the memory module selection to allow for pipeline-line operation.

In this type of tycom, 64 megabytes of DRAM per board can be loaded, and 8 memory boards can be installed per system, thus retaining a total capacity of 512 megabytes. It is designed to operate up to 8-way (interleaving control information) interleaving, which is set automatically according to the number and location of the memory at power-on.

However, since it operates as a memory module having a large capacity of 64 megabytes per board, performance is hindered when an odd memory board is mounted.

In addition, the memory board includes a system bus 4, a register 4a for temporarily storing an address entered through the system bus 4, as shown in FIG. The DRAM driver 4c in the memory bank, the multiplexer 4b for selecting and outputting a memory address from one of the addresses output from the register 4a, and the address selection line A25 for bank selection are provided. It was a connected configuration.

The multiplexer section 4c is an interleaving-related address path, and specifically, as shown in FIG. 3, four mega (22 bits) address lines are connected to input terminals of the three multiplexers 15, 16, and 17. Two banks are serially used using the bank selection address line A25.

On the other hand, the data path configuration of the conventional memory board is a part that is responsible for the interface signal between the system bus 4 and the memory as shown in FIG. 4, and corresponds to the system bus of Tycom, Drive / Receive. An RP standard interface 7 and an input queue 8 that can be temporarily stored when a memory bank is in use to respond to successive memory accesses or behave the same when the bus is in use, and An output queue 9, an input buffer 11 and an output buffer 12 that provide data paths corresponding to writing / reading data on the DRAM, the input queue 8 and the output queue 9, and By controlling the input buffer 11 and the output buffer 12, the memory controller 10 for controlling the signals (RAS, CAS ...) used in the DRAM and the entire state machine of the memory, and the DRAM In part It is physically composed of two banks (each 32 megabytes) 13 and 14.

According to the above-described configuration, a method of designing the input queue 8 independently in bank units and a method of designing the input buffer 11 with a register separately at a rear end thereof are performed.

In the method in which the input queue 8 is independently designed in bank units, the input buffer is stored at the rear end by storing data separately by referring to the bank selection address signal when the input queue 8 is loaded. There are performance advantages over designing the registers separately, but the disadvantage of using expensive chips is that they double the first-in first-out (FIFO) data.

In addition, the method of designing the input buffer 11 with the registers at the rear end separately uses the input queue 8 in common. However, when using the same bank in succession, the previous buffer may be used even if the next address is not the same bank. The advantage is that all data is accessed after it has been serviced.

In addition, a latch must be used at the rear end in accordance with the timing.

Thus, the conventional memory is composed of two banks, but functionally configured to operate as one module.

Therefore, even if the locality of the program exists, the response speed is approximately twice as late in time because it is composed of a single memory controller (DMC) even if it is a continuous address (i.e., a different bank can be used). There was a problem that the performance of the overall system is degraded.

That is, even if information of another bank exists in the queue, there is a problem in that it waits until the previous data is completely serviced and then remains in the queue after the data is completely resolved.

An object of the present invention is to provide an on-board interleaving apparatus and method of a main memory in a multiprocessor system for improving performance of a system by implementing interleaving in a memory board to solve the above problems.

The present invention for achieving the above object will be described in detail with reference to the accompanying drawings.

In the data path configuration of the present invention, as shown in FIG. 5, the corresponding address and data temporarily stored in the input queue 18 in accordance with the input / output signal of the RP standard interface 17 connected to the system bus 4 are shown. To store the first and second banks 23 and 24 in the first and second banks 23 and 24 or when the system bus 4 is in use. The first and second input buffers 21a and 21b serving as data paths corresponding to the respective data paths 23 and 24 and corresponding addresses and data read out from the first and second banks 23 and 24 are output queues 19. The first and second output buffers 22a and 22b serving as temporary storage data paths for output to the AlpS standard interface 17, corresponding addresses inputted and outputted from the first bank 23, and First to selectively control the first input buffer 21a or the first output buffer 22a, which is a path corresponding to data. Second memory controller 20b for selectively controlling the second input buffer 21b or the second output buffer 22b in correspondence with the corresponding address and data input and output from the memory controller 20a and the second bank 24. It is composed of

The first and second memory controllers 20a and 20b operate as independent memory controllers to simultaneously access the two banks 23 and 24 at any one time.

The address path related to interleaving for storing data in a certain place by the data path is inputted to the input terminals of the three multiplexes 25, 26 and 27, respectively, as shown in FIG. It consists of a path for selecting each memory address (mem_a2, mem_a1, mem_a0) through each of the multiplexers, and the bank selection address line uses A3.

Unlike the conventional design of the input queue 8 independently in bank units, in the present invention, a method of designing a pressure cue as shown in FIG. 7A according to the number of banks and FIG. A method of sharing an input queue as shown in the drawing will be described.

First, the method of designing the input queue 18 corresponding to the number of banks includes the steps of latching an address from the system bus 4 (S1) and a board selection step of decoding and determining whether the address is suitable for the magnetic memory board. A bank selection determination step of determining which bank is selected from one bank (first bank) and the other bank (second bank) when the information is valid for the magnetic memory board according to the board selection relation (S2) and (S2). (S3), when the one bank is selected by the bank selection determining step (S3), loading the address and data into the input queue of the bank (S4), and the state of the first memory controller 20a. When the other bank is selected by the step S5 for allowing the machine to operate, sending data to access the DRAM of the one bank (i.e., data service), and the bank selection judging step S3. In that bank Loading a corresponding address and data into an input queue (S7), operating a state machine of the second memory controller 20b (S8), and sending data to access the DRAM of the other bank (i.e., , Data service) step S9.

The operation by these steps first latches an address from the system bus 4, decodes this address as appropriate for the magnetic memory board, and identifies which bank is selected if valid information is available for the memory board.

Then, the corresponding address and related information are loaded in the input queue of the corresponding bank, the corresponding machine of the memory controller is operated, and then the DRAM of the corresponding bank is accessed.

Next, the method of sharing the input queue includes the steps of latching an address from the system bus (S10), a board selection step (S11) for decoding and determining whether the address is suitable for a magnetic memory board, and the board. Loading information into the input queue when the information is valid for the magnetic memory board by the selecting step S11, and when the information is valid for the magnetic memory board by the board selecting step S11, one bank and the other bank. A bank selection determination step (S13) of determining which bank is selected, and a step (S14) of checking whether a corresponding bank is in use when one bank is selected by the bank selection determination step (S13), and A step S15 of operating the state machine of the first memory controller 20a when the one bank is not in use by the checking step S14; and sending data to access the DRAM of the one bank. (I.e., data service) step (S16), and when the other bank is selected by the bank selection determination step (S13), checking whether or not the corresponding bank is in use (S17), and checking step (S18). And sending data (ie, data service) to access the DRAM of the other bank (S19).

The operation by the above steps is performed by first latching the address and related information from the system bus 4, and immediately after the address decoding is effective in the magnetic memory in the same way as the method of designing the input queue corresponding to the number of banks. To 18).

After retrieving which bank information is selected, it checks whether the corresponding bank is in use or not (state machine check), and sends data to access the DRAM of the corresponding bank when not in use.

At this time, a flip-flop is latched in front of the buffer drive in bank units to make it valid during data service.

In addition, the above two methods can share the output buffer in common, and even if there is one cycle difference in the boss cycle, the data drive time can be shared by the output queue 19 because the difference in time is usually one cycle.

As described above, in the present invention, interleaving can have a great effect when there is locality of a program. However, in the case of Tycom, the CPU is designed to be twice the bandwidth of the bus. Cache line size of the processing unit. Whenever the central processing unit accesses the memory, there is continuous addressing.

Therefore, the memory access time improvement (data service time) that is about twice as much as when a single memory is installed in the current system can be expected.

Claims (6)

The corresponding addresses and data temporarily stored in the input queue 18 are stored in the first and second banks 23 and 24 according to an input / output signal from the Alp (RP) stepdard interface 17 connected to the system bus 4. For example, when the first and second banks 23 and 24 are in use or when the system bus 4 is in use, a data path corresponding to each of the first and second banks 23 and 24 is used. Outputs the first and second input buffers 21a and 21b and the corresponding addresses and data read from the first and second banks 23 and 24 to the Alpstad interface 17 through an output queue 19. The first and second output buffers 22a and 22b, each of which are stored temporarily for storing data, and the first input buffer 21a which is a path corresponding to the corresponding address and data input and output from the first bank 23, respectively. Alternatively, the first memory control unit 20a selectively controls the first output buffer 22a and input / output the second bank 24. The address and data in correspondence to the first input buffer (21b) or the second output buffer, the second memory control section (20b) within the interleaved unit of the main memory in a multiprocessor system consisting of a board for selectively controlling the (22b). 2. The on-board interleaving apparatus of the main memory device according to claim 1, wherein the first memory controller (20a) selects the first bank (23) as one address lime (A3). 2. The on-board interleaving apparatus of a main memory device according to claim 1, wherein said first memory control section (20b) selects said second bank (24) by either address line (A3). The multiprocessor of claim 1, wherein the first and second memory controllers 20a and 20b are independently configured to simultaneously access the first and second banks 23 and 24 at any one time. In-board interleaving of main memory in the system. When the input queue 18 is designed to correspond to the number of banks, a step of latching an address from the system bus 4 (S1), and a board selection step of decoding and determining whether the address is suitable for the magnetic memory board (S2). And a bank selection determining step S3 for determining which bank is selected from one bank and the other bank when the information is valid for the magnetic memory board by the board selection step S2, and the bank selection determining step S3. (S4) loading a corresponding address and data to an input queue of the corresponding bank when one bank is selected by the step S), and operating the state machine of the first memory controller 20a (S5), and Sending data to access the DRAM of one bank (S6), and when the other bank is selected by the bank selection determination step (S3), the corresponding address and data is loaded in the input queue of the bank. In the multi-processor system comprising the step (S7) and the step (S8) to operate the state machine of the second memory controller 20b and the step (S9) of sending data to access the DRAM of the other bank On-board interleaving method of main memory. When the input queue is shared, latching an address from the system bus (S10), a board selection step (S11) for decoding and determining whether the address is suitable for a magnetic memory board, and the board selection step (S11). If it is valid information on the magnetic memory board by the step of loading to the input queue (S12), and if the information is valid on the magnetic memory board by the board selection step (S11) which bank of the one bank and the other bank is selected A bank selection determination step (S13) for judging, a step (S14) of checking whether a corresponding bank is in use when a bank is selected by the bank selection determination step (S13), and the checking step (S14). When the one bank is not in use, allowing the state machine of the first memory controller 20a to operate (S15), and sending data to access the DRAM of the one bank (S16). If the other bank is selected by the bank selection judging step S13, checking whether the corresponding bank is in use (S17); and if the other bank is not in use by the checking step S17, the second memory. And a step (S18) of operating the state machine of the control unit (20b) and sending data to access the DRAM of the other bank (S19).