JPS63311548A - Cache memory controlling system - Google Patents

Abstract

PURPOSE:To sharply improve the performance of a data processing system, by setting write data in a write data buffer in a cache memory device even when a cache error occurs. CONSTITUTION:When a cache error occurs in the course of storing access, the content of a write data buffer register 21 is written in a cache memory 20 after a move-in registering operation is made or the combined result of write data and move-in data in the unit of byte in accordance with the content of a byte mark is written in the cache memory 20 while the registering operation is carried on. Therefore, even if a cache error occurs, an instruction processor 1 can make so called throwing-off control which causes storing access to be completed by setting the write data in the write data buffer register 21 in a cache memory device. Thus the performance of this system can be improved sharply.

Description

[Detailed Description of the Invention] [Table of Contents] (Existing industrial fields of application, Prior art and problems to be solved by the invention, Means for solving the problems, Actions, Examples, Effects of the invention [Summary]) Swap method In a cache memory device controlled by
), or in addition to the write data buffer register,
A byte mark register, a circuit for selecting the write data buffer register and a register storing move-in data from the main memory (MS) in units of bytes based on the contents of the byte mark register are provided. At the time of a miss, after the move-in registration operation, the contents of the write data buffer register are written to the cache memory, or during the registration operation, the write data and move-in data are written in byte units based on the contents of the byte mark. The combined result is written to the cache memory.

[Industrial application field]

The present invention relates to a control method for writing write data to a cache memory at the time of a cache miss in a cache memory device controlled by a swap method.

Conventionally, one of the means to improve the processing performance of data processing systems is the cache memory method.This method is based on the locality of the address distribution of the program executed by the instruction processing unit. A block-by-block copy from the main memory (MS) is stored in a cache memory that has a smaller storage capacity than the main memory (MS) but is faster than the main memory (MS). In response to a memory request, if the corresponding data exists in the cache memory, the cache memory responds to the memory request, thereby shortening the apparent access time to the main memory (MS).
This improves the processing capacity of the data processing system.

However, when the block containing the data to be accessed does not exist in the cache memory, it is necessary to move the block from the main memory (MS) into the cache memory, and during this time the instruction processing unit is in a waiting state for processing. Therefore, the current situation is that the reduction in processing performance caused by the cache miss cannot be ignored, and a cache memory control method is required that reduces the reduction in processing performance at the time of the cache miss.

[Prior art and problems to be solved by the invention] FIG. 5 is a diagram illustrating a conventional cache memory control system.

In this figure, for convenience of explanation, data lines for performing move-in are mainly shown.

One of the cache memory control methods is a swap method.

In this swap method, (1) At the time of reading, if the data block requested by the instruction processing device 1 is in the cache memory 2o, it is read immediately from the cache memory 2o, but if a cache miss occurs, the main After moving the corresponding block from storage device (MS) 3 into an empty block, the corresponding block is read.

(2) At the time of writing, if the data block requested by the instruction processing device 1 is in the cache memory 20, is it possible to write it (for example, in a multiprocessor system, another processor rewrites the block in question)? (In this case, it becomes impossible to write)
If it is possible, write to that block, but if it is not possible, write after notifying the cache memory of another processor that the block is invalidated in order to acquire the write right.

However, when a cache miss occurs, the main memory (
MS) From step 3, move the corresponding block into an empty block and write it there.

In the move-in operation at the time of a cache miss during read or write, if there is no free block in the cache memory, the block to be evicted is searched for using the well-known LRII mechanism, and the contents of the block are transferred to the main memory (M
S) If the block does not match the corresponding block in 3, the block is moved out to the main storage device (MS) 3 and moved in there; however, if it matches, the block is moved in as an overwrite.

When the instruction processing device 1 attempts to perform a store access to such a swap type cache memory 20 and a cache miss occurs, the instruction processing device 1 retains the store data and performs the move-in operation as described above. Wait for the move-in data from the main storage device (MS) 3 to be registered on the cache memory 20, and after the registration operation is completed, store it to the cache memory 20 (specifically, byte According to the contents of the mark, the byte mark was stored only for the 1 byte.

In general, store accesses in data processing occur at a frequency of, for example, once every few instructions, so there is a problem in that performance degradation due to cache misses during store accesses may be excessive.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional drawbacks, it is an object of the present invention to provide a method for reducing performance degradation due to cache misses during store access in a data processing system equipped with a cache memory controlled by a swap method. be.

[Means for solving problems]

FIG. 1 is a diagram showing an example of the configuration of a cache memory control method according to the present invention.

In the present invention, (1) In a cache memory device controlled by a swap method, a buffer register 21 that holds write data;

The write data buffer register 21 and the main memory (
MS) 3, and a data bus 22a that writes the output of the write data selection circuit 22 to the cache memory 20, and sends the write data to the write data buffer register 21. After the cache registration operation in response to a cache miss, the write data buffer register 21
The configuration is such that the contents of are written to the cache memory 20.

(2) In order to write the contents of the write data buffer register 21 to the cache memory 20 at the time of the above cache miss, in addition to the write data buffer register 21 that holds the write data, transfer from the main storage device (MS) 3 is required. a move-in data register 24 that holds data; a byte mark register 23 that holds a byte mark indicating the validity/invalidity of the write data in units of bytes; A circuit 2 that selects the contents of the register 21 and the move-in data register 24 in byte units.
2 and the output of the byte selection circuit 22 is stored in the cache memory 2.
0, the write data is held in the write data buffer register 21, the byte mark is held in the byte mark register 23, and during the cache registration operation in response to a cache miss, the register 21 and , the contents of the register 24 are selected and synthesized in byte units by the selection circuit 22' and written into the cache memory 20.

[Effect]

That is, according to the present invention, in a cache memory device controlled by a swap method, a buffer register that holds write data, and the contents of the write data buffer register and move-in data from the main memory f (MS) are stored. Alternatively, in addition to the write data buffer register, a byte mark register, the write data buffer register, and a main memory (MS) may be provided.
) and a circuit that selects the register storing move-in data from the byte mark register in byte units according to the contents of the byte mark register, and when a cache miss occurs in a store access, the write data buffer is selected after the move-in registration operation. Write the contents of the register to cache memory, or
During the registration operation, the write data and move index are combined in byte units based on the contents of the byte mark, and the result is written to the cache memory, so the instruction processing device can avoid cache misses. Even if a write access occurs, by setting the write data to the write data buffer register in the cache memory device, the store access can be completed, so-called push-out control, and the performance of the data processing system can be greatly improved. effective.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 1 is a diagram showing an example of the configuration of the cache memory control method of the present invention, where (a) shows the case where write data is stored in the cache memory after move-in registration, and (b) shows the case where write data is stored in the cache memory during move-in registration. This shows a case where write data and move-in data are combined and the combined data is stored in a cache memory. Fig. 2 is a diagram showing an example of the overall configuration of a data processing system, and Fig. 3 is a diagram showing an example of the overall configuration of a data processing system. 1 is a diagram showing an example of the present invention in the form of a time chart, and (a) and (b) respectively correspond to (a) and (b) in FIG.
FIG. 4 is a diagram showing an embodiment of a write data synthesis circuit, and corresponds to write data buffer register 21.b) in FIG. Move-in register 24. Write data selection circuit 22. Or byte selection circuit 22''.

Byte mark register 23 is the necessary means to implement the invention. Note that the same reference numerals indicate the same objects throughout the figures.

Hereinafter, the cache memory control method using the push-out method according to the present invention will be explained with reference to FIGS. 1 to 4.

First, the basic operation of cache memory control using the above-mentioned push-out method will be explained with reference to FIGS. 1 to 3(a).

In FIG. 2(a), when the instruction processing device 1 performs a memory store, it turns on the cache request signal, simultaneously outputs a memory address to the address line (1), and writes write data to the data line (1). At the same time, a bite mark is output on the bite mark line.

Upon receiving the memory address, the cache control device 2 searches a tag memory (not shown) to determine whether the data block to be accessed is registered in the cache memory 20.

As a result, if the data block is registered (cache hit), the cache air address is output to the cache memory 20, the write enable is turned on, and the write data output to the data line (1) is output. is stored in bytes based on the byte marks on the byte mark line.

If the data block is not registered in the cache memory 20 (cache miss), a memory request signal is output to the main memory device (MS) 3 and a main memory address is output to the address line (2), and the data The instruction processing device 1 completes the store access by setting the write data output on line (1) in the write data buffer register 21 shown in FIG. The so-called "pull-off method" is used to move on to processing. Thereafter, the cache control device 2 autonomously performs the following operations.

That is, the requested data block is output from the main memory device (MS) 3 to the data line (2) after the access time of the main memory device (MS) 3, and is set in the mooge-in data register 2. Ru.

Next, the write data selection circuit 22 selects the move-in data register 2, and the requested data block is output to the data line (1) and written to the cache memory 20.

After the data transfer from the main storage device (MS) 3 is completed, the write data selection circuit 22 selects the write data buffer register 21, and the write data is output to the data line (1) and transferred to the cache memory. 20, it is overwritten in byte units based on the above-mentioned byte mark information.

A time chart showing the above operation is shown in Figure 3 (
a).

In cycle 1, the instruction processing device 1 outputs a cache request signal, a memory address to the address line (1), and write data to the data line (1), and the write data is set in the write data buffer register 21.

And cycle n+1 after the access time.

In cycle n+2, the requested data from main memory (MS) 3 has a data bus width (for example, 8 bytes wide).
is sent in units of move-in data register 24.
and is transferred to the corresponding block of the cache memory 20 in cycle n+2 and cycle n+3, respectively.

Generally, the cache memory 20 is divided into fixed-length blocks of about several tens of bytes, and the cache memory 20 is divided into fixed-length blocks of about several dozen bytes.
) If the bus width of the data line (2) from 3 is 8 bytes, which is shorter than the block length of the cache memory 20, as described above, data transfer is performed several times. This example shows that data transfer was performed twice.

Then, in cycle n+3, the data transfer is completed, and in the first cycle n+4, the contents of the write data buffer register 21 are written in byte units to the corresponding area of the cache memory 20 based on the byte-margin information. Ru.

In the store push-out method described above, as described above, the instruction processing unit 1 is released when write data is set in the write data buffer register 21, thereby avoiding performance degradation associated with move-in operations in the event of a cache miss. However, the requested data can be moved in from the main storage device (MS) 3 and registered in the cache memory 20,
In addition, when writing the contents of the write data buffer register to the cache memory 20, the data line (1) to the cache memory 20 is used, so depending on the state of the instruction processing device, there may be a competition for the data line (1). may occur.

Generally, the cache control device 2 has a higher priority over the data line (1), and in the event of a conflict, the instruction processing device 1 enters a waiting state, causing a decrease in performance.

In the "push-out method" explained in FIGS. 1 to 3(a), move-in data from the main storage device (MS) 3 is registered in the cache memory 20, and then write data is written to the cache memory 20. However, as a result,
Focusing on the fact that some data in the move-in data is data that will be overwritten by the write data, the bytes of the move-in data that will not be overwritten and the write data are combined and stored in the cache memory 20 at the same time. By writing, it is possible to omit the cycle of writing the write data after the move-in described above.

FIGS. 1 to 3(b) show improvements to the above-mentioned "push-out method" based on the above-mentioned principle. Below, the corresponding figure 1 ~
The improved cache memory control method will be explained with reference to FIG. 3(b) and FIG. 4.

In general, cache memory can be read/written in units of several bytes (for example, 8 bytes) at a time in order to perform high-speed operations.

On the other hand, since the instruction processing device l performs processing in byte units, when transferring write data to the cache memory 20, control information called a byte mark is output together with the write data, and the cache memory 20 transfers the write data It is configured to write only the byte indicated by the byte mark.

Furthermore, as mentioned above, the move-in data to the cache memory 20 is composed of blocks of 32 bytes/64 bytes, etc., but the write operation described above This is performed on, for example, 8 bytes.

Usually, the move-in data is edited so that the word (8 bytes) to be written is at the beginning according to the write address, and the main memory (MS)
In some cases, the data may be moved in sequentially from the first 8 bytes of the block boundary.

With respect to such a cache memory, the improved cache memory control operation using the above-mentioned push-out method will be explained below with reference to FIGS. 1 to 3(b).

In FIG. 2(b), the instruction processing device! ! When 1 performs a memory store, it turns on the cache request signal, simultaneously outputs a memory address to the address line (1), outputs write data to the data line (1), and writes a byte mark to the byte mark line. Output.

When the cache control device 2 receives the memory address, it searches a storage circuit called a tag memory (not shown) and checks whether data is registered in the cache memory 20.

As a result, if the data is registered, the cache address is output to the cache memory 20, the write enable is turned on, and the data output to the data line 1 is written in byte units according to the above-mentioned byte mark. Write with .

Furthermore, when data is not registered in the cache memory 20 (that is, at the time of a cache miss), the main memory (M
S) Output the memory request signal to 3 and the main memory address from the address line (2), and convert the write data output to the data line (1) into the write data shown in FIG. 1(b). The buffer register 21 is set, and the byte mark of the byte mark line is set in the byte mark register 23.

Thereafter, move-in data is output from the main memory (MS) 3 to the data line (2) and set in the move-in data register 24.

Next, the byte selection circuit 22 whose embodiment is shown in FIG.
' is the write data buffer register 21 according to the value of the byte mark register 23.

Select one of the move-in data registers 24 in byte units (for example, if the byte mark is °1°, select the write data buffer register 21;
If it is 0, select the move-in data register 24) and write the combined write data (8 bytes),
It is output to the data line (1) via the data bus 22a and written to the cache memory 20.

FIG. 3(b) shows a case where no data is registered in the cache memory 20, and at the beginning of the move-in data,
14 is a time chart when data corresponding to the write address is being retrieved.

In this figure, in cycle 1, a cache request signal, a write address, write data, and a byte mark are output from the instruction processing device 1, and the write data is set in the write data buffer register 21.

Then, in cycle n+1, the main memory! (1'
Move-in data is sent from IS) 3 and set in the move-in data register 24, and in cycle n+2, the contents of the write data buffer register 21 and the contents of the move-in data register 24 are changed according to the value of the byte mark register 23. The byte selection circuit 22' synthesizes the data in byte units and writes it into the cache memory 20.

The remainder of the move-in data is set in the move-in data register 24 in cycle n+2, and written to the cache memory 20 in cycle n+3.

As mentioned above, move-in data is stored in the main memory (MS)
Regardless of the write address sent in step 3, if the write address is sent in order from the first word (8 bytes) at the boundary of the block that includes the write address, the lower bits of the write address are used to write the move-in data. The word to be composed of (
8 bytes) and enter the selected word (8 bytes) as
It is necessary to select one of the bite marks and make it function to synthesize write data.

As described above, the present invention provides a cache memory device controlled by the swap method, in which the cache control device includes:
A write data buffer register is provided to hold write data, and when a cache miss occurs during memory store, the instruction processing device sets the write data in the write data buffer register, assumes that the write access is completed, and then Then, the main memory (MS) is autonomously stored within the cache control device.
), and after registering the move-in data sent from the main memory (MS) in the cache memory, write the write data, or write the move-in data during the registration operation. The feature is that it is combined with the write data and written to the cache memory.

〔Effect of the invention〕

As described above in detail, the cache memory control method of the present invention is applicable to a cache memory device controlled by the swap method, which includes a buffer register that holds write data, and a main function that controls the contents of the write data buffer register. A circuit for selecting move-in data from the storage device (MS) is provided, or, in addition to the write data buffer register, a byte mark register, the write data buffer register, and a circuit for selecting move-in data from the main storage device (MS) are provided. A circuit is provided that selects a register storing move-in data in byte units based on the contents of the byte mark register, so that when a cache miss occurs in a store access,
After the move-in registration operation, the contents of the write data buffer register are written to the cache memory, or the contents of the write data buffer register are written to the cache memory during the move-in registration operation.

The move-in data is combined with the move-in data in bytes based on the contents of the byte mark, and the result is written to the cache memory. Therefore, even if a cache miss occurs, the instruction processing unit will not be able to write the write data. By setting it in the write data buffer in the cache memory device, it is possible to complete the store access, so-called push-out control, which has the effect of significantly improving the performance of the data processing system.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of a cache memory control method according to the present invention. FIG. 2 is a diagram showing an example of the overall configuration of a data processing system. FIG. 3 is a time chart showing an embodiment of the present invention. FIG. 4 is a diagram showing an embodiment of a write data synthesis circuit. FIG. 5 is a diagram explaining a conventional cache memory control method. It is. In the drawings, 1 is an instruction processing device, and 2 is a cache control device. 20 is a cache memory. 21 is a write data buffer register. 22 is a write data selection circuit. 22゛ is a byte selection circuit. This is a move-in data register. 3 is the main memory (MS). are shown respectively. , Thu, ig's Yaya Rue Kumori h・1 odd V Kahe no Kime 1
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Claims (2)

[Claims] (1) In a cache memory device controlled by the swap method, a buffer register (21) that holds write data, the write data buffer register (21), and data from the main memory (MS) (3) are It includes a write data selection circuit (22) to select, and a data bus (22a) to write the output of the write data selection circuit (22) to the cache memory (20), and the write data is transferred to the write data buffer register (21). ), and after a cache registration operation in response to a cache miss, the contents of the write data buffer register (21) are written to the cache memory (20). (2) In order to write the contents of the write data buffer register (21) to the cache memory (20) at the time of the cache miss, in addition to the write data buffer register (21) that holds the write data, the main storage ( A move-in data register (24) that holds the transfer data from MS) (3), a byte mark register (23) that holds a byte mark that indicates the validity/invalidity of the write data in bytes, and the byte mark register. (23), a circuit (22') that selects the contents of the write data buffer register (21) and the move-in data register (24) in units of bytes; and the byte selection circuit (22'). ) and a data bus (22a) for writing the output of the cache memory (20),
Write data to the above write data buffer register (2
1), and the byte mark register (2).
3), and during the cache registration operation in response to a cache miss, the contents of the register (21) and register (24) are selected and combined in byte units by the selection circuit (22') and stored in the cache memory ( 20). The cache memory control method according to claim 1, wherein the cache memory control method writes to the cache memory.