JPS63311548A - Cache memory controlling system - Google Patents

Cache memory controlling system

Info

Publication number
JPS63311548A
JPS63311548A JP62148218A JP14821887A JPS63311548A JP S63311548 A JPS63311548 A JP S63311548A JP 62148218 A JP62148218 A JP 62148218A JP 14821887 A JP14821887 A JP 14821887A JP S63311548 A JPS63311548 A JP S63311548A
Authority
JP
Japan
Prior art keywords
write data
cache memory
cache
error occurs
data buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP62148218A
Other languages
Japanese (ja)
Other versions
JPH0677240B2 (en
Inventor
Masayuki Okada
Tsuyoshi Mori
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62148218A priority Critical patent/JPH0677240B2/en
Publication of JPS63311548A publication Critical patent/JPS63311548A/en
Publication of JPH0677240B2 publication Critical patent/JPH0677240B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE: To sharply improve the performance of a data processing system, by setting write data in a write data buffer in a cache memory device even when a cache error occurs.
CONSTITUTION: When a cache error occurs in the course of storing access, the content of a write data buffer register 21 is written in a cache memory 20 after a move-in registering operation is made or the combined result of write data and move-in data in the unit of byte in accordance with the content of a byte mark is written in the cache memory 20 while the registering operation is carried on. Therefore, even if a cache error occurs, an instruction processor 1 can make so called throwing-off control which causes storing access to be completed by setting the write data in the write data buffer register 21 in a cache memory device. Thus the performance of this system can be improved sharply.
COPYRIGHT: (C)1988,JPO&Japio
JP62148218A 1987-06-15 1987-06-15 Cache memory control circuit Expired - Fee Related JPH0677240B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62148218A JPH0677240B2 (en) 1987-06-15 1987-06-15 Cache memory control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62148218A JPH0677240B2 (en) 1987-06-15 1987-06-15 Cache memory control circuit

Publications (2)

Publication Number Publication Date
JPS63311548A true JPS63311548A (en) 1988-12-20
JPH0677240B2 JPH0677240B2 (en) 1994-09-28

Family

ID=15447919

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62148218A Expired - Fee Related JPH0677240B2 (en) 1987-06-15 1987-06-15 Cache memory control circuit

Country Status (1)

Country Link
JP (1) JPH0677240B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8327101B2 (en) 2008-02-01 2012-12-04 International Business Machines Corporation Cache management during asynchronous memory move operations
US8356151B2 (en) 2008-02-01 2013-01-15 International Business Machines Corporation Reporting of partially performed memory move

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8327101B2 (en) 2008-02-01 2012-12-04 International Business Machines Corporation Cache management during asynchronous memory move operations
US8356151B2 (en) 2008-02-01 2013-01-15 International Business Machines Corporation Reporting of partially performed memory move

Also Published As

Publication number Publication date
JPH0677240B2 (en) 1994-09-28

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees