JPH0677240B2 - Cache memory control circuit - Google Patents

Description

DETAILED DESCRIPTION [Table of Contents] Outline Industrial field of application Conventional techniques and problems to be solved by the invention Means for solving problems Problems Working Example Example of the invention [Summary] Controlled by swap method A cache memory device for storing write data, contents of the write data buffer register and main memory device (MS)
And a circuit for selecting the move-in data from, or in addition to the write data buffer register,
A cache is provided by providing a byte mark register, the write data buffer register, and a register for accumulating move-in data from the main storage device (MS) on a byte-by-byte basis based on the contents of the byte mark register. At the time of a miss, after the move-in registration operation, the contents of the write data buffer register are written to the cache memory, or during the registration operation, the write data and the move-in data are written in byte units based on the contents of the byte mark. The synthesized result is written in the cache memory.

[Industrial application field]

The present invention relates to a control circuit for writing write data to a cache memory when a cache miss occurs in a cache memory device controlled by a swap method.

Conventionally, a cache memory system has been adopted as one means for improving the processing capacity of a data processing system.

This is based on the locality of the address distribution of the program executed by the instruction processing unit, and the range of addresses where the locality is seen is set as one block, and a copy in block units from the main memory unit (MS) is performed. The storage capacity is smaller than that of (MS) but is held in a high-speed cache memory, and when the corresponding data exists in the cache memory in response to a memory request from the instruction processing device, the cache memory is By responding, the apparent access time to the main memory (MS) is shortened, and the processing capacity of the data processing system is improved.

However, when the block including the data to be accessed does not exist in the cache memory, it is necessary to move the block from the main storage device (MS) to the cache memory, and the instruction processing device waits for processing during that time. The current situation is that the reduction in processing capacity due to the cache miss cannot be ignored, and a cache memory control circuit that reduces the reduction in processing capacity at the time of the cache miss is required.

[Problems to be solved by conventional technology and invention]

FIG. 5 is a diagram for explaining a conventional cache memory control method.

In this figure, for convenience of explanation, the data lines for performing the move-in are mainly shown.

A swap method is one of the cache memory control methods.

In the swap method, (1) at the time of read, if the data block requested by the instruction processing device 1 exists in the cache memory 20, it is immediately read from the cache memory 20, but when a cache miss occurs, the main memory After moving the relevant block from the device (MS) 3 to an empty block, the relevant block is read.

(2) At the time of writing, if the data block requested by the instruction processing device 1 exists in the cache memory 20,
Check whether it is writable (for example, in a multiprocessor system, another processor may rewrite the block, and in this case, it becomes unwritable),
If it is possible, the block is written, but if it is not possible, the cache memory of another processor is notified of the invalidation of the block to obtain the write right, and then the block is written.

However, when a cache miss occurs, the corresponding block is moved from the main memory (MS) 3 to an empty block and written there.

In the move-in operation at the time of a cache miss at the time of reading or writing, when there is no free block in the cache memory, the eviction block is searched by the well-known LRU mechanism, and the content of the corresponding block is the main storage device (MS) 3
If the block does not match the corresponding block, the block is moved out to the main storage device (MS) 3 and moved in there. If they match, the block is moved in by overwriting.

When the instruction processing device 1 tries to execute a store access to the swap type cache memory 20,
When a cache miss occurs, the instruction processing device 1
After the store data is held, the move-in operation waits for the move-in data from the main storage device (MS) 3 to be registered in the cache memory 20, and after the registration operation is completed, the cache memory 20 However, according to the content of the byte mark, only the byte whose byte mark is “1” is stored.

In general, a store access in data processing occurs, for example, once every several instructions, so that there is a problem that the performance degradation due to a cache miss during the store access is excessive.

In view of the above-mentioned conventional drawbacks, it is an object of the present invention to provide a cache memory control circuit for reducing the deterioration of performance due to a cache miss at the time of store access in a data processing system including a cache memory controlled by a swap method. To do.

[Means for solving problems]

FIG. 1 is a diagram showing a configuration example of a cache memory control system of the present invention.

In the present invention, (1) in a cache memory device controlled by a swap method, a write data buffer register 21 that holds write data from the instruction processing device 1, the write data buffer register 21, and a main memory device (MS ) Move-in data register 24 that holds move-in data from 3
Write data selection circuit 22 for selecting the data of the write data selection circuit 22 and a data path 22a for writing the output of the write data selection circuit 22 to the cache memory 20. The write data from the instruction processing device 1 is transferred to the write data buffer register. When it is held in 21, the write access is completed after the store access operation of the instruction processing device 1 is completed and the move-in data is registered in the cache memory 20 in response to the cache miss generated in response to the store access operation. The contents of the data buffer register 21 are autonomously written to the cache memory 20.

(2) To write the contents of the write data buffer register 21 to the cache memory 20 at the time of the above cache miss, in addition to the write data buffer register 21 that holds the write data, transfer from the main memory (MS) 3 A move-in data register 24 for holding data, a byte mark register 23 for holding a byte mark indicating valid / invalid of the write data in byte units, and the write data buffer in response to the contents of the byte mark register 23. The instruction processing device 1 comprises a register 21, a circuit 22 'for selecting the contents of the move-in data register 24 in byte units, and a data path 22a for writing the output of the byte selection circuit 22' to the cache memory 20. Write data to the write data buffer register 21 and byte marks to the byte mark register. When held in 23, the store access operation of the instruction processing device 1 is completed, and the move-in data is autonomously registered in the cache memory 20 in response to the cache miss generated in response to the store access operation. The contents of the write data buffer register 21 and the move-in data register 24 are stored in the byte selection circuit 2
2'Select byte by byte, synthesize and cache memory 20
It is configured to write to.

[Action]

That is, according to the present invention, in the cache memory device controlled by the swap method, the buffer register holding the write data, the content of the write data buffer register, and the move-in data from the main storage device (MS) are selected. Or a byte mark register, the write data buffer register, and a register that stores move-in data from the main memory (MS) in addition to the write data buffer register. A circuit for selecting the content of the mark register in units of bytes is provided to write the content of the write data buffer register to the cache memory after the move-in registration operation at the time of a cache miss in the store access, or during the registration operation. Write data and move-in data based on the contents of the byte mark. Then, since the result of combining in byte unit is written in the cache memory, the instruction processing device can
By setting the write data in the write data buffer register in the cache memory device, so-called push-out control that completes the store access can be performed, and there is an effect that the performance of the data processing system can be significantly improved.

〔Example〕

 Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 described above is a diagram showing a configuration example of the cache memory control circuit of the present invention, (a) shows a case where write data is stored in the cache memory after move-in registration, and (b) shows during move-in registration. FIG. 2 shows a case where write data and move-in data are combined and the combined data is stored in a cache memory. FIG. 2 is a diagram showing an example of the overall configuration of a data processing system, and FIG. FIG. 4 is a diagram showing an embodiment of the present invention in a time chart, where (a) and (b) respectively correspond to (a) and (b) of FIG. 1, and FIG. 4 shows write data. FIG. 3 is a diagram showing an embodiment of a synthesizing circuit, in which the write data buffer register 21, the move-in register 24, the write data selecting circuit 22, or the byte selecting circuit 22 'and the byte mark register 23 of FIG. Carry out It is a necessary means for still,
Throughout the drawings, the same reference numerals denote the same objects.

The cache memory control circuit according to the present invention will be described below with reference to FIGS. 1 to 4.

First, the basic operation of the cache memory control by the above-mentioned release method will be described with reference to FIGS.

In FIG. 2 (a), when the instruction processing device 1 performs a memory store, the cache request signal is turned on, the memory address is output to the address line (1) at the same time, and the write data is written to the data line (1). And the byte mark is output to the byte mark line.

When the cache control device 2 receives the memory address, it searches a tag memory (not shown) to check whether or not the data block to be accessed is registered in the cache memory 20.

As a result, when the data block is registered (cache hit), the cache address is output to the cache memory 20, the write enable is turned on, and the write data output to the data line (1) is output. Is stored in byte units based on the byte mark of the byte mark line.

If the data block is not registered in the cache memory 20 (cache miss), the memory request signal is output to the main memory device (MS) 3 and the main memory address is output to the address line (2) to output the data. The write data output to the line (1) is set in the write data buffer register 21 shown in FIG.
Completes the store access and moves to the processing of the next instruction,
The so-called "push-through method" is adopted. After that, the cache controller 2 autonomously performs the following operations.

That is, the requested data block is output from the main memory device (MS) 3 to the data line (2) and set in the move-in data register 24 after the access time of the main memory device (MS) 3. .

Next, the write data selection circuit 22 selects the move-in data register 24, the requested data block is output to the data line (1), and is written in the cache memory 20.

After the data transfer from the main memory device (MS) 3 is completed, the write data selection circuit 22 selects the write data buffer register 21, the write data is output to the data line (1), and the cache memory 20 is overwritten on a byte-by-byte basis based on the byte mark information.

FIG. 3 (a) shows the above operation in a time chart.

In cycle 1, the instruction processing device 1 outputs the cache request signal, the memory address to the address line (1) and the write data to the data line (1), and the write data is set in the write data buffer register 21.

Then, in the cycle n + 1 and the cycle n + 2 after the access time, the request data from the main memory (MS) 3 is sent out in units of the data bus width (for example, 8 byte width) and set in the move-in data register 24. Then, in cycles n + 2 and n + 3, they are transferred to the corresponding blocks of the cache memory 20, respectively.

In general, the cache memory 20 is divided into fixed-length blocks of about several tens of bytes, and the main storage device (MS) 3
As described above, when the bus width of the data line (2) is from 8 bytes, which is shorter than the block length of the cache memory 20, the data transfer is performed several times. In this example, it is shown that the data transfer is performed twice.

Then, in cycle n + 3, the data transfer is completed, and in the next cycle n + 4, the contents of the write data buffer register 21 are written in the corresponding area of the cache memory 20 in byte units based on the information of the byte mark. It

In the above-mentioned "push-off method" of the store, as described above, the instruction processing device 1 is released when the write data is set in the write data buffer register 21, so that the performance deterioration due to the move-in operation at the cache miss is avoided. However, the requested data is moved in from the main memory (MS) 3 and registered in the cache memory 20, and the contents of the write data buffer register are stored in the cache memory 20.
When writing to, the data line (1) to the cache memory 20 is used, so depending on the state of the instruction processing device,
A race condition for the data line (1) may occur.

In general, the cache controller 2 has a higher priority on the data line (1), and when a contention occurs, the instruction processor 1 enters a waiting state, which causes a deterioration in performance.

In the “push-off method” described with reference to FIGS. 1 to 3A, the move-in data from the main storage device (MS) 3 is registered in the cache memory 20, and then the write data is written in the cache memory 20. However, as a result, paying attention to the fact that a part of the data in the move-in data is data that is overwritten by the write data, and the bytes that are not overwritten in the move-in data and the write data are combined. Then, by simultaneously writing to the cache memory 20, the cycle of writing the write data after the move-in can be omitted.

1 to 3 (b) is an improvement of the above-mentioned "push-off method" based on the above-mentioned gist. Hereinafter, FIG.
The improved cache memory control system will be described with reference to FIG. 3 (b) and FIG.

Generally, the cache memory can be read / written in units of several bytes (for example, 8 bytes) at a time in order to operate at high speed.

On the other hand, since the instruction processing device 1 performs processing in units of bytes, when transferring write data to the cache memory 20, together with the write data, control information called a byte mark is output, and the cache memory 20 writes the write data. Only the bytes indicated by the byte mark are written.

Further, the move-in data to the cache memory 20 is configured in the unit of block having 32 bytes / 64 bytes etc. as one block as described above. , For example, for 8 bytes.

Then, in general, corresponding to the write address, the word to be written (8 bytes) is edited so that the move-in data is formed at the head, and depending on the main storage device (MS), the block In some cases, the move-in may be sequentially performed from the first 8 bytes of the boundary of the.

With respect to such a cache memory, the operation of the improved cache memory control by the above-mentioned release method will be described below with reference to FIGS. 1 to 3B.

In FIG. 2 (b), when the instruction processing device 1 performs a memory store, the cache request signal is turned on, the memory address is output to the address line (1) at the same time, and the write data is written to the data line (1). Is output, and the byte mark is output to the byte mark line.

When the cache control device 2 receives the memory address, it searches a storage circuit called a Doug memory (not shown) to check whether or not data is registered in the cache memory 20.

As a result, when the data is registered, the cache address is output to the cache memory 20, the write enable is turned “on”, and the data output to the data line 1 is converted into byte units according to the above byte mark. To write.

If data is not registered in the cache memory 20 (that is, when there is a cache miss), the main memory (MS)
3, the memory request signal and the main storage address from the address line (2) are output, and the write data output to the data line (1) is transferred to the write data buffer register 21 shown in FIG. 1 (b). The byte mark of the byte mark line is set in the byte mark register 23.

After that, the move-in data from the main memory (MS) 3
Output to the data line (2) Move-in data register 24
Is set to.

Next, the byte selection circuit 22 'whose embodiment is shown in FIG.
According to the value of the byte mark register 23, the write data buffer register 21 and the move-in data register 24
Either of them is selected in byte unit (for example, if the byte mark is “1”, the write data buffer register 21 is selected, and if the byte mark is “0”, the move-in data register 24 is selected). The combined write data (8 bytes) is output to the data line (1) via the data path 22a and written to the cache memory 20.

FIG. 3B is a time chart in the case where the data is not registered in the cache memory 20 and the data corresponding to the write address is fetched at the beginning of the move-in data.

In the figure, in cycle 1, the instruction processing unit 1 outputs a cache request signal, a write address, write data, and a byte mark, and the write data is set in the write data buffer register 21.

Then, in cycle n + 1, the main memory (MS) 3
Move-in data is sent from the write-in data register 24 and set in the move-in data register 24. In cycle n + 2, the contents of the write-data buffer register 21 and the contents of the move-in data register 24 are determined by the byte selection circuit according to the value of the byte mark register 23. At 22 ', they are combined byte by byte and written to the cache memory 20.

The rest of the move-in data is set in the move-in data register 24 in cycle n + 2, and written in the cache memory 20 in cycle n + 3.

As described above, the move-in data is stored in the main storage device (MS) 3
Irrespective of the write address sent to the first write address, when the data is sent in order from the first word (8 bytes) at the boundary of the block including the write address, the lower bits of the write address are used to write the move-in data. Select a word to be combined (8 bytes) and select either the write data buffer register 21 or the move-in data register 24 for the selected word (8 bytes) in byte units according to the value of the byte mark. Then, it is necessary to function so as to synthesize the write data.

As described above, the present invention provides, in a cache memory device controlled by a swap method, in a cache control device,
A write data buffer register for holding the write data is provided, and the instruction processing unit sets the write data in the write data buffer register at the time of a cache miss at the time of memory store and considers that the write access is completed. The so-called "out-of-the-box" method is used, and thereafter, the main memory (MS) is autonomously operated in the cache controller.
Memory request and write-in data sent from the main memory (MS) is registered in the cache memory and then write data is written, or write-in data and write-in data are written during the registration operation. It is characterized in that it is combined with data and written to the cache memory.

〔The invention's effect〕

As described above in detail, in the cache memory control circuit of the present invention, in the cache memory device controlled by the swap method, the buffer register for holding the write data, the contents of the write data buffer register, and the main storage device ( Or a move-in data from the main memory device (MS), or a byte mark register, the write data buffer register, and a move-in data from the main storage device (MS) in addition to the write data buffer register. A register for accumulating data and a circuit for selecting the contents of the byte mark register in units of bytes are provided so that the contents of the write data buffer register are cached after the move-in registration operation at the time of a cache miss in store access. Write to the memory or write data during the registration operation The result of combining the save-in data and the byte mark based on the content of the byte mark is written to the cache memory.
Even if a cache miss occurs, the instruction processing device can perform so-called push-off control, which completes the store access by setting the write data in the write data buffer in the cache memory device, thus improving the performance of the data processing system. There is an effect that can be greatly improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a configuration example of a cache memory control circuit of the present invention, FIG. 2 is a diagram showing an example of the overall configuration of a data processing system, and FIG. 3 is an embodiment of the present invention. FIG. 4 is a diagram showing an example in a time chart, FIG. 4 is a diagram showing an embodiment of a write data synthesizing circuit, and FIG. 5 is a diagram explaining a conventional cache memory control system. In the drawings, 1 is an instruction processor, 2 is a cache controller, 20 is a cache memory, 21 is a write data buffer register, 22 is a write data selection circuit, 22 'is a byte selection circuit, 24 is a move-in data register, and 3 is Main memory (MS), respectively.

Claims (2)

[Claims] 1. A cache memory device controlled by a swap method, a write data buffer register (21) for holding write data from an instruction processing device (1), the write data buffer register (21), and a main memory. A write data selection circuit (22) for selecting the data of the move-in data register (24) holding the move-in data from the device (MS) (3), and the output of the write data selection circuit (22) is a cache memory. When the write data from the instruction processing device (1) is held in the write data buffer register (21), a store access operation of the instruction processing device 1 is performed. The move-in data cache memory (2) which is completed and responds to the cache miss generated in response to the store access operation.
A cache memory control circuit characterized by autonomously writing the contents of the write data buffer register (21) to the cache memory (20) after a registration operation to 0). 2. The content of the write data buffer register (21) is cached in the cache memory (20) when the cache miss occurs.
A write data buffer register (21) for holding the write data, a move-in data register (24) for holding the move-in data from the main storage device (MS) (3), and A byte mark register (23) that holds a byte mark that indicates the validity / invalidity of write data in byte units, and the write data buffer register (21) and move-in corresponding to the contents of the byte mark register (23). A data path (22a) for writing the output of the byte selection circuit (22 ') into the cache memory (20), and a circuit (22') for selecting the contents of the data register (24) in byte units. When the write data from the instruction processing unit (1) is held in the write data buffer register (21) and the byte mark is held in the byte mark register (23), To complete the store access operation decrees processing apparatus (1), the cache memory of the move-in data in response to a cache miss has occurred in response to the store access operation (2
During the registration operation to 0), the contents of the write data buffer register (21) and the move-in data register (24) are autonomously selected and combined in byte units by the byte selection circuit (22 '). The cache memory control circuit according to claim 1, wherein writing is performed in the cache memory (20).