JPH06243037A - Data look-ahead device - Google Patents

Abstract

PURPOSE:To provide a data look-ahead device where the number of access times from a processor is small in the data look-ahead device used in a multi- processor system sharing a storage device. CONSTITUTION:A buffer memory 6 accumulating data which are read out for each of blocks which are previously set from an external storage device, a buffer address memory 8 accumulating the address of data stored in the buffer memory 6 and a specified address memory 9 accumulating a part of address in data stored in the buffer memory 6 are provided. When the processor 1 reads out data corresponding to the address accumulated in the specified address memory 9 from the buffer memory 6, a memory management part 7 invalidates the buffer memory 6. Since the data look-ahead device invalidates the buffer memory by itself by access to the specified address, the processor 1 need not give a buffer memory invalidating instruction. Then, the number of the access times of the processor 1 is reduced and a high speed operation becomes possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system comprising a plurality of processors and a storage device accessed from them, and when the processor reads data from the storage device, the data is prefetched and stored in a buffer memory, The present invention relates to a data prefetching device for efficiently reading data from a processor.

[0002]

2. Description of the Related Art FIG. 6 is a diagram showing a configuration of a conventional data prefetching device and connections between the data prefetching device, a processor, and a storage device. In FIG. 6, 1a and b are processors, 2a and b are data read-ahead devices respectively connected to the processors 1a and b, 3 is a common bus to which the data read-ahead devices 2a and b are connected, and 4 is a data read-ahead device 2a, b. ,
The storage devices 5 accessed from the processors 1a and b via the common bus 3 are connected to the processors 1a and 1b, respectively, and an exclusive control mechanism for controlling access right to the storage device 4 among the plurality of processors 1a and b, Reference numerals 6a and 6b are buffer memories constituting the data pre-reading device 2, 7a and b are constituents of the data pre-reading device 2, and buffer memory managers for controlling the buffer memories 6a and 6b are provided. 8a and 8b are data pre-reading devices 2a and b. And a buffer address memory for storing the address of the data of the storage device 4 stored in the buffer memories 6a and 6b.

Next, the operation will be described. The data read-ahead device is a device that stores a part of the data (area for communication) of the storage device in advance in a buffer memory in order to perform communication between a plurality of processors.

When any of the processors 1a and 1b accesses the storage device 4, first, the exclusive control mechanism 5
Acquire the right to use the storage device 4. If not,
I will wait until I can get it.

When the processor 1a acquires the usage right,
The processor 1a accesses the storage device 4 via the data prefetching device 2a, but the data stored in the buffer memory 6a of the data prefetching device 2a is rewritten by the other processor 1b. It may be different from the current data in the storage device 4.

Therefore, the processor 1a invalidates the buffer memory 6a. To invalidate means to initialize the memory, for example, to set a flag indicating that the data is valid to 0. After invalidating the buffer memory 6a, read access to the storage device 4 is performed, and the exclusive control right is released when the read access is completed.

[0007]

In the conventional data prefetching apparatus, the processor 1 is used to invalidate the buffer memory 6a of the data prefetching apparatus 2a as described above.
a needs to instruct the data prefetching device 2a to invalidate, so that the data prefetching device 2 is transferred from the processor 1a.
There is a problem that the number of times of access to a increases.

For example, for the data prefetching device 2a, 4
An example will be described in which the processor 1a, which accesses in byte units, reads 16 bytes from the address 0 of the storage device 4 via the common bus 3.

As shown in FIG. 7, (1) an access right is acquired by exclusive control. (2) Disable the buffer memory. (3) Read 4 bytes of the storage device (address 0) (buffer miss) (4) Transfer data from the storage device to the buffer memory. (5) Read 4 bytes from the storage device (address 4). (6) Read 4 bytes from the storage device (address 8). (7) Read 4 bytes of the storage device (address 12). (8) 16-byte read processing from address 0 is performed in the order of releasing the exclusive control right.

In the case of FIG. 7, the number of times of access from the processor 1a to the data prefetching device 2a is as follows (2), (3),
(5), (6), and (7) a total of 5 times. When a small amount of data is frequently accessed, these accesses cause an overhead, resulting in deterioration of processing performance.

The present invention has been made in order to solve the above problems, and sets a part of addresses in advance as a specific address in an area of a storage device for performing data communication between a plurality of processors. The read access to the specific address is intended to reduce the number of accesses from the processor to the data prefetching device by invalidating the data buffer by the data prefetching device itself.

[0012]

The invention according to claim 1 is
A buffer memory for storing the data read from the external storage device for each preset block, a first address memory for storing the address of the data stored in the buffer memory, and data stored in the buffer memory Second part of a predetermined part of the address of the
Address memory and memory management means for managing the buffer memory, and when the data corresponding to the address stored in the second address memory is read from the buffer memory, the contents of the buffer memory are It invalidates.

According to a second aspect of the present invention, there is provided a buffer memory for storing data read from an external storage device for each preset block, and a first address for storing an address of the data stored in the buffer memory. A memory, a second address memory that stores a predetermined part of the address of the data stored in the buffer memory, and a memory management unit that manages the buffer memory. This is equivalent to the size of a block of data read from an external storage device.

According to a third aspect of the invention, when data other than the data corresponding to the address stored in the second address memory is read from the buffer memory,
It accepts a request to invalidate the contents of the buffer memory.

[0015]

According to the first aspect of the invention, the memory management means detects that the data corresponding to the address stored in the second address memory is read from the buffer memory. Invalidates the contents of the buffer memory and transfers data.

In the second aspect of the invention, the buffer memory is not invalidated, and only the data transfer is performed.

In the invention according to claim 3, the memory management means detects that the data corresponding to the address stored in the second address memory is read from the buffer memory, whereby the data prefetching device itself is To invalidate the contents of the buffer memory and to accept a request to invalidate the contents of the buffer memory when data other than the data corresponding to the address stored in the second address memory is read from the buffer memory. To invalidate.

[0018]

【Example】

Embodiment 1 An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of a data prefetching device according to the present invention and a connection between the data prefetching device, a processor, and a storage device. In FIG. 1, 1a and b are processors, 2a and b are data pre-reading devices connected to the processors 1a and 1b, 3 is a common bus to which the data pre-reading devices 2a and 2b are connected, and 4 is data pre-reading devices 2a and 2b. ,
A storage device 5, which is accessed from the processors 1a and b via the common bus 3, is connected to the processors 1a and b, and an exclusive control mechanism for controlling access right to the storage device 4 among the plurality of processors 1a and b, 6a, b is the data prefetching device 2
a and b are buffer memories that store data from the storage device 4, 7a and b are data look-ahead devices 2a and b, and a buffer memory management unit that controls the buffer memories 6a and b, and 8a and b are A buffer address memory that configures the data prefetching devices 2a and 2b and stores an address of data of the storage device 4 stored in the buffer memories 6a and 6b, and 9a and 9b are specific address memories that store specific addresses.

Next, the operation will be described. FIG. 2 shows an outline of the read processing of the processor. (1) When any of the processors 1a and 1b accesses the storage device 4, first, the exclusive control mechanism 5 acquires the right to use the storage device 4. If you cannot get it, you will have to wait until you can get it.

(2) When the processor 1a acquires the usage right, the processor 1a accesses the storage device 4 via the data prefetching device 2a. Since data is regularly read based on the specific address of the data block, the processor 1a first reads from the data of the specific address. Here, the specific address refers to, for example, a leading address and an ending address for each data block of a fixed size, for example, a 16-byte boundary.

(3) However, since the data stored in the buffer memory 6a of the data prefetching device 2a is rewritten by the other processor 1b, the current data in the storage device 4 is read. It is stored in the buffer memory 6a. (4) Release the control right acquired in (1).

By the way, in the above (2), it is necessary to invalidate (initialize) the data in the buffer memory 6a. However, the data read-ahead device of the present invention uses "accessed" as a condition for invalidating the buffer memory. It is necessary to explicitly invalidate the buffer memory for the data read-ahead device of the processor by adding not only "the data of the address is not in the buffer memory" but also the condition of "reading to a specific address". Disappear.

In other words, in the data prefetching apparatus according to the present invention, the data prefetching apparatus 2a itself automatically invalidates the buffer memory 6a, so that the processor 1
It is not necessary for a to instruct the data prefetching device 2a to invalidate, so that the data prefetching device 2a
It is possible to suppress an increase in the number of accesses to a.

Next, the above operation will be described in more detail using a specific example. For example, it is assumed that the processor 1a, which accesses the data prefetching device 2a in units of 4 bytes, reads 16 bytes from the address 0 of the data block of the storage device 4 via the common bus 3.

As shown in FIG. 3, processing is performed according to the following steps. (1) Acquire an access right by exclusive control. (2) Read 4 bytes of the storage device (address 0). The processor 1a performs a 4-byte read to the address 0 of the storage device 4 with respect to the data prefetch device 2a.
Since address 0 is the start address of the block and is a specific address, the buffer memory management unit 7a detects this and invalidates the buffer memory 6a. The invalidation is performed, for example, by initializing the memory and setting a flag indicating that the data is valid to 0. As a result, the processor 1a cannot read the data at the address 0 (buffer miss), so that the data is read from the storage device 4 as shown below.

(3) Data is transferred from the storage device 4 to the buffer memory 6a. The buffer memory management unit 7a prefetches 16 bytes from the address 0 to the storage device 4 via the common bus 3. That is, as shown in FIG. 5, by transferring a partial area 14 (data block), which is an area for communication between processors defined in the address map 12 of the storage device 4, to the buffer memory, The area 14 of becomes the content 11 of the buffer memory 6a. The area 13 is an area provided in the area 12 of the storage device 4 in which the area 14 can be provided. In FIG. 5, the area 14 is placed at the head (address 0).

At this time, the buffer address is set in the buffer address memory 8a corresponding to the contents 11 stored in the buffer memory 6a. That is, as shown in FIG. 4, the size of the block is 16 bytes, and addresses 0, 4, 8, and 12 are set in correspondence with reading of data every 4 bytes. When the block size is 32 bytes or more, addresses 16, 20, ... Are set in addition to the above addresses. Of these, address 0 and address 16 in the figure are specific addresses. In FIGS. 4 and 5, the address is in hexadecimal notation. After the data transfer is completed, the processor 1a reads 4 bytes (15 area in FIG. 4) from the address 0.

(4) Read 4 bytes of the storage device (address 4). When the processor 1a reads 4 bytes to the address 4, the buffer memory management unit 7a knows that the buffer 4 has been hit because the address 4 is written in the buffer address memory 8a, and the buffer memory management unit 7a writes to the storage device 4. No access is performed and the data corresponding to the address 4 of the buffer memory 6a is returned to the processor 1.

(5) Read 4 bytes of the storage device (address 8). This is the same as the read at the address 4. (6) Read 4 bytes from the storage device (address 12). This is the same as the read at the address 4. (7) Release of exclusive control right The exclusive control mechanism 5 releases the exclusive control right and transfers the usage right to another processor.

In the case of FIG. 3, the number of accesses from the processor 1a to the data prefetching device 2a is the same as the above (2), (4),
This is a total of 4 times of (5) and (6), and since the data invalid instruction is not necessary, it is reduced once compared to the conventional data prefetching device.
The same applies to the case of the processor 1b.

The read operation from the buffer memory 6a is as described above, but the write operation is performed by the processor 1a by the store-through method of writing the data in the buffer memory 6a and also in the storage device 4. However, the write operation is not limited to this method and may be a store-in method.

The specific address is the processor 1a, 1
b, the data read-ahead devices 2a and 2b may be different. Further, the number of processors may be three or more.

Embodiment 2 Although the size of the buffer memory is larger than the size of the prefetch data in the above example, the size of the buffer memory may be set to be equal to the size of the prefetch data block. It suffices to set the pre-read data from the storage device and register the corresponding address of the buffer address without performing the process of invalidating. This is because the same effect as invalidation can be obtained by data transfer.

For example, when the data block is 16 bytes, the size of the buffer memories 6a and 6b is set to 16 bytes. Then, when the processor 1a reads the specific address, the data is transferred from the storage device 4 to the buffer memory 6a immediately. Then, since the contents of the buffer memory 6a are all the same as the latest contents of the storage device 4, it is not necessary to invalidate the buffer 6a.

Also in this case, as in the case of FIG. 3, the number of accesses is (2) 4-byte read of the storage device (address 0), and data transfer is performed without invalidation by accessing a specific address. (4) 4-byte read of storage device (address 4) (5) 4-byte read of storage device (address 8) (6) 4-byte read of storage device (address 12): 4 times in total Reduces once compared to the device.

Third Embodiment In the above example, the processor always accesses from a specific address, but when accessed from an address other than the specific address, it has a function of accepting only a request for invalidating the contents of the buffer memory. By having it, it is possible to deal with the case where the processor accesses other than a specific address.

[0037]

As described above, according to the first and third aspects of the present invention, the instruction for invalidating the buffer memory in the data prefetching device is realized in the form of access to a specific address. The number of accesses to the data prefetching device can be reduced.

Further, according to the invention of claim 2, since the capacity of the buffer memory in the data prefetching device is made equal to the size of the data block, the invalidation instruction is not necessary, and the processor reads data from the data prefetching device. It is possible to reduce the number of times of access.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a data prefetching device according to the present invention.

FIG. 2 is a diagram showing an embodiment of a read process of a processor according to the present invention.

FIG. 3 is a diagram showing details of an embodiment of a read process of the processor according to the present invention.

FIG. 4 is a diagram showing an example of an address map of a buffer memory according to the present invention.

FIG. 5 is a diagram showing an example of an address map of a storage device according to the present invention.

FIG. 6 is a diagram showing a conventional data prefetching device.

FIG. 7 is a diagram showing details of a read process of a conventional processor.

[Explanation of symbols]

 1 Processor 2 Data Lookahead Device 3 Common Bus 4 Storage Device 5 Exclusive Control Mechanism 6 Buffer Memory 7 Buffer Memory Management Section 8 Buffer Address Memory 9 Specific Address Memory

Claims (3)

[Claims] 1. A buffer memory for storing data read from an external storage device for each preset block, a first address memory for storing an address of the data stored in the buffer memory, and the buffer memory. A second address memory that stores a predetermined part of the address of the data stored in, and data corresponding to the address stored in the second address memory are read from the buffer memory, A data pre-reading device comprising: memory management means for invalidating the contents of the buffer memory and transferring data for each block from the external storage device to the buffer memory. 2. A buffer memory that stores data read from an external storage device for each preset block and stores a buffer memory having a capacity equivalent to the size of the block and an address of the data stored in the buffer memory. A first address memory for storing, and a second address memory for storing a predetermined part of the address of the data stored in the buffer memory.
Memory for transferring the data for each block from the external storage device to the buffer memory when the data corresponding to the addresses stored in the address memory and the second address memory are read from the buffer memory. A data prefetching device comprising: management means. 3. When the data other than the data corresponding to the address stored in the second address memory is read from the buffer memory, it receives a request to invalidate the contents of the buffer memory. The data prefetching device according to claim 1.